Datasheet > IS61DDB22M18A-250B4

IS61DDB22M18A-250B4

更新时间： 2024-11-18 19:43:43

品牌	Logo	应用领域
美国芯成 - ISSI		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
29页	453K
描述
DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165

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IS61DDB22M18A-250B4 技术参数

生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.3
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	37748736 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	1.89 V
最小供电电压 (Vsup)：	1.71 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm	Base Number Matches：	1

IS61DDB22M18A-250B4 数据手册

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IS61DDB22M18A

IS61DDB21M36A

2Mx18, 1Mx36

ADVANCED INFORMATION

JULY 2012

36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

FEATURES

DESCRIPTION

The 36Mb IS61DDB21M36A and IS61DDB22M18A are

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have a common I/O

bus. The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed. Refer to

the Timing Reference Diagram for Truth Table for a

description of the basic operations of these DDR-II (Burst of

2) CIO SRAMs.



1Mx36 and 2Mx18 configuration available.

On-chip delay-locked loop (DLL) for wide data valid

window.



Common I/O read and write ports.

Synchronous pipeline read with self-timed late write

operation.



Double Data Rate (DDR) interface for read and

write input ports.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.



Fixed 2-bit burst for read and write operations.

Clock stop support.

The following are registered internally on the rising edge of

the K clock:

Two input clocks (K and K#) for address and control

registering at rising edges only.



Read/write address

Read enable

Write enable

Byte writes for first burst address

Data-in for first burst address



Two input clocks (C and C#) for data output control.

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.



+1.8V core power supply and 1.5V to 1.8V VDDQ,

used with 0.75V to 0.9V VREF.

The following are registered on the rising edge of the K#

clock:



HSTL input and output interface.

Registered addresses, write and read controls, byte

writes, data in, and data outputs.



Byte writes for second burst address

Data-in for second burst address



Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock.



Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

During the burst read operation, the data-outs from the first

bursts are updated from output registers of the second rising

edge of the C# clock (starting one and half cycles later after

read command). The data-outs from the second bursts are

updated with the third rising edge of the C clock. The K and

K# clocks are used to time the data-outs whenever the C and

C# clocks are tied high.



Programmable impedance output drivers via 5x

user-supplied precision resistor.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

7/05/2012

12 3 4 5 6 7...29

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与IS61DDB22M18A-250B4相关器件

型号	品牌	获取价格	描述	数据表
IS61DDB22M18A-250B4L	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB22M18A-300M3L	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB22M36	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36-250M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36-250M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36-300M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36-300M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36-300M3LI	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36A	ISSI	获取价格	Common I/O read and write ports
IS61DDB22M36A-300B4LI	ISSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

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