Datasheet > IS61DDB24M18A

IS61DDB24M18A

更新时间： 2024-11-19 01:20:19

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
29页	770K
描述
Common I/O read and write ports

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数据手册

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IS61DDB24M18A 数据手册

IS61DDB24M18A

IS61DDB22M36A

4Mx18, 2Mx36

AUGUST 2014

72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

FEATURES

DESCRIPTION

The 72Mb IS61DDB22M36A and IS61DDB24M18A are

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have a common I/O

bus. The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed. Refer to

the Timing Reference Diagram for Truth Table for a

description of the basic operations of these DDR-II (Burst of

2) CIO SRAMs.



2Mx36 and 4Mx18 configuration available.

On-chip delay-locked loop (DLL) for wide data valid

window.



Common I/O read and write ports.

Synchronous pipeline read with self-timed late write

operation.



Double Data Rate (DDR) interface for read and

write input ports.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.



Fixed 2-bit burst for read and write operations.

Clock stop support.

The following are registered internally on the rising edge of

the K clock:

Two input clocks (K and K#) for address and control

registering at rising edges only.



Read/write address

Read enable

Write enable

Byte writes for first burst address

Data-in for first burst address



Two input clocks (C and C#) for data output control.

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.



+1.8V core power supply and 1.5V to 1.8V VDDQ,

used with 0.75V to 0.9V VREF.

The following are registered on the rising edge of the K#

clock:



HSTL input and output interface.

Registered addresses, write and read controls, byte

writes, data in, and data outputs.



Byte writes for second burst address

Data-in for second burst address



Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock.



Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

During the burst read operation, the data-outs from the first

bursts are updated from output registers of the second rising

edge of the C# clock (starting one and half cycles later after

read command). The data-outs from the second bursts are

updated with the third rising edge of the C clock. The K and

K# clocks are used to time the data-outs whenever the C and

C# clocks are tied high.



Programmable impedance output drivers via 5x

user-supplied precision resistor.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

08/15/2014

12 3 4 5 6 7...29

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与IS61DDB24M18A相关器件

型号	品牌	获取价格	描述	数据表
IS61DDB251236A	ISSI	获取价格	Fixed 2-bit burst for read and write operations
IS61DDB41M18A	ISSI	获取价格	1Mx18, 512Kx36 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M36-250M3	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M36A	ISSI	获取价格	Synchronous pipeline read with late write operation
IS61DDB41M36A-300M3LI	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB41M36C-250M3L	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB41M36C-300M3	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB41M36C-333M3	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB41M36C-333M3L	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB41M36C-333M3LI	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

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