Datasheet > IS61DDB42M18C-300B4L

IS61DDB42M18C-300B4L

更新时间： 2024-11-18 19:42:15

品牌	Logo	应用领域
美国芯成 - ISSI		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
30页	829K
描述
DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

IS61DDB42M18C-300B4L 技术参数

生命周期：	Active	包装说明：	LBGA,
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.69
最长访问时间：	0.45 ns	JESD-30 代码：	R-PBGA-B165
长度：	15 mm	内存密度：	37748736 bit
内存集成电路类型：	DDR SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	1.89 V	最小供电电压 (Vsup)：	1.71 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	13 mm
Base Number Matches：	1

IS61DDB42M18C-300B4L 数据手册

浏览型号IS61DDB42M18C-300B4L的Datasheet PDF文件第2页

浏览型号IS61DDB42M18C-300B4L的Datasheet PDF文件第3页

浏览型号IS61DDB42M18C-300B4L的Datasheet PDF文件第4页

浏览型号IS61DDB42M18C-300B4L的Datasheet PDF文件第5页

浏览型号IS61DDB42M18C-300B4L的Datasheet PDF文件第6页

IS61DDB42M18C

IS61DDB41M36C

2Mx18, 1Mx36

36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

MARCH 2016

DESCRIPTION

FEATURES

The 36Mb IS61DDB41M36C and IS61DDB42M18C are

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have a common I/O

bus. The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed. Refer to

the Timing Reference Diagram for Truth Table for a

description of the basic operations of these DDR-II (Burst of

4) CIO SRAMs.



1Mx36 and 2Mx18 configuration available.

On-chip delay-locked loop (DLL) for wide data valid

window.



Common I/O read and write ports.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for read and

write input ports.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.



Fixed 4-bit burst for read and write operations.

Clock stop support.

Two input clocks (K and K#) for address and control

registering at rising edges only.

The following are registered internally on the rising edge of

the K clock:



Two input clocks (C and C#) for data output control.



Read/write address

Read enable

Write enable

Byte writes for burst addresses first and third

Data-in for burst addresses first and third

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.



+1.8V core power supply and 1.5V to1.8V VDDQ,

used with 0.75V to 0.9V VREF.



HSTL input and output interface.

The following are registered on the rising edge of the K#

clock:

Registered addresses, write and read controls, byte

writes, data in, and data outputs.



Byte writes for burst addresses second and fourth

Data-in for burst addresses second and fourth



Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock. Two full

clock cycles are required to complete a write operation.



Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array



Programmable impedance output drivers via 5x

user-supplied precision resistor.

During the burst read operation, the data-outs from the first

and third bursts are updated from output registers of the

second and third rising edges of the C# clock (starting on and

half cycles later after read command). The data-outs from the

second and fourth bursts are updated with the third and

fourth rising edges of the C clock. The K and K# clocks are

used to time the data-outs whenever the C and C# clocks are

tied high. Two full clock cycles are required to complete a

read operation.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

12 3 4 5 6 7...30

中文翻译

下载PDF

与IS61DDB42M18C-300B4L相关器件

型号	品牌	获取价格	描述	数据表
IS61DDB42M18C-300M3I	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB42M18C-333B4	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB42M36	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36-250M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36-250M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36-300M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36-300M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36A	ISSI	获取价格	Synchronous pipeline read with late write operation
IS61DDB44M18-250M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB44M18-250M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs

与IS61DDB42M18C-300B4L相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

18
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

43
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

38

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61DDB42M18C-300B4L

IS61DDB42M18C-300B4L 技术参数

IS61DDB42M18C-300B4L 数据手册

与IS61DDB42M18C-300B4L相关器件

与IS61DDB42M18C-300B4L相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61DDB42M18C-300B4L

IS61DDB42M18C-300B4L 技术参数

IS61DDB42M18C-300B4L 数据手册

与IS61DDB42M18C-300B4L相关器件

与IS61DDB42M18C-300B4L相关文章

您还可以找

您在本页遇到什么问题？