Datasheet > IS61DDB42M18C-250B4I

IS61DDB42M18C-250B4I

更新时间： 2024-11-21 19:42:15

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IS61DDB42M18C

IS61DDB41M36C

2Mx18, 1Mx36

36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

MARCH 2016

DESCRIPTION

FEATURES

The 36Mb IS61DDB41M36C and IS61DDB42M18C are

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have a common I/O

bus. The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed. Refer to

the Timing Reference Diagram for Truth Table for a

description of the basic operations of these DDR-II (Burst of

4) CIO SRAMs.



1Mx36 and 2Mx18 configuration available.

On-chip delay-locked loop (DLL) for wide data valid

window.



Common I/O read and write ports.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for read and

write input ports.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.



Fixed 4-bit burst for read and write operations.

Clock stop support.

Two input clocks (K and K#) for address and control

registering at rising edges only.

The following are registered internally on the rising edge of

the K clock:



Two input clocks (C and C#) for data output control.



Read/write address

Read enable

Write enable

Byte writes for burst addresses first and third

Data-in for burst addresses first and third

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.



+1.8V core power supply and 1.5V to1.8V VDDQ,

used with 0.75V to 0.9V VREF.



HSTL input and output interface.

The following are registered on the rising edge of the K#

clock:

Registered addresses, write and read controls, byte

writes, data in, and data outputs.



Byte writes for burst addresses second and fourth

Data-in for burst addresses second and fourth



Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock. Two full

clock cycles are required to complete a write operation.



Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array



Programmable impedance output drivers via 5x

user-supplied precision resistor.

During the burst read operation, the data-outs from the first

and third bursts are updated from output registers of the

second and third rising edges of the C# clock (starting on and

half cycles later after read command). The data-outs from the

second and fourth bursts are updated with the third and

fourth rising edges of the C clock. The K and K# clocks are

used to time the data-outs whenever the C and C# clocks are

tied high. Two full clock cycles are required to complete a

read operation.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

12 3 4 5 6 7...30

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与IS61DDB42M18C-250B4I相关器件

型号	品牌	获取价格	描述	数据表
IS61DDB42M18C-250B4LI	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-250M3L	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-250M3LI	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-300B4I	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB42M18C-300B4L	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-300M3I	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB42M18C-333B4	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB42M36	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36-250M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36-250M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs

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