Datasheet > 存储 > SRAM> IS61DDB42M18-250M3L

IS61DDB42M18-250M3L

更新时间： 2024-11-18 13:08:55

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路静态存储器双倍数据速率时钟
页数	文件大小	规格书
26页	515K
描述
2MX18 DDR SRAM, 0.35ns, PBGA165, 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FBGA-165

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IS61DDB42M18-250M3L 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	Factory Lead Time：	13 weeks 6 days
风险等级：	5.67	Is Samacsys：	N
最长访问时间：	0.35 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	17 mm	内存密度：	37748736 bit
内存集成电路类型：	DDR SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大待机电流：	0.2 A
最小待机电流：	1.71 V	子类别：	SRAMs
最大压摆率：	0.55 mA	最大供电电压 (Vsup)：	1.89 V
最小供电电压 (Vsup)：	1.71 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	15 mm	Base Number Matches：	1

IS61DDB42M18-250M3L 数据手册

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36 Mb (1M x 36 & 2M x 18)

ISSI

DDR-II (Burst of 4) CIO Synchronous SRAMs

May 2005

• Two echo clocks (CQ and CQ) that are delivered

simultaneously with data.

Features

• 1M x 36 or 2M x 18.

• +1.8V core power supply and 1.5, 1.8V V_DDQ

used with 0.75, 0.9V V_REF

• On-chip delay-locked loop (DLL) for wide data

valid window.

• HSTL input and output levels.

• Common I/O read and write ports.

• Registered addresses, write and read controls,

byte writes, and data outputs.

• Synchronous pipeline read with late write opera-

tion.

• Full data coherency.

• Double data rate (DDR-II) interface for read and

• Boundary scan using limited set of JTAG 1149.1

functions.

write input ports.

• Fixed 4-bit burst for read and write operations.

• Clock stop support.

• Byte write capability.

• Fine ball grid array (FBGA) package

- 15mm x 17mm body size

- 1mm pitch

• Two input clocks (K and K) for address and con-

trol registering at rising edges only.

• Two input clocks (C and C) for data output con-

trol.

- 165-ball (11 x 15) array

• Programmable impedance output drivers via 5x

user-supplied precision resistor.

Description

The 36Mb IS61DDB41M36 and IS61DDB42M18

are synchronous, high-performance CMOS static

random access memory (SRAM) devices. These

SRAMs have a common I/O bus. The rising edge of

K clock initiates the read/write operation, and all

internal operations are self-timed. Refer to the

Timing Reference Diagram for Truth Table on p.8

for a description of the basic operations of these

DDR-II (Burst of 4) CIO SRAMs.

• Data-in for burst addresses 2 and 4

Byte writes can change with the corresponding data-

in to enable or disable writes on a per-byte basis. An

internal write buffer enables the data-ins to be regis-

tered one cycle later than the write address. The first

data-in burst is clocked one cycle later than the write

command signal, and the second burst is timed to

the following rising edge of the K clock. Two full

clock cycles are required to complete a write opera-

tion.

Read and write addresses are registered on alter-

nating rising edges of the K clock. Reads and writes

are performed in double data rate. The following are

registered internally on the rising edge of the K

clock:

During the burst read operation, at the first and third

bursts the data-outs are updated from output regis-

ters off the second and fourth rising edges of the C

clock (starting 1.5 cycles later). At the second and

fourth bursts, the data-outs are updated with the

third and fifth rising edges of the corresponding C

clock (see page 9). The K and K clocks are used to

time the data-outs whenever the C and C clocks are

tied high. Two full clock cycles are required to

complete a read operation

• Read and write addresses

• Address load

• Read/write enable

• Byte writes for burst addresses 1 and 3

• Data-in for burst addresses 1 and 3

The following are registered on the rising edge of

the K clock:

The device is operated with a single +1.8V power

supply and is compatible with HSTL I/O interfaces.

• Byte writes for burst addresses 2 and 4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.

07/09/04

12 3 4 5 6 7...26

中文翻译

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与IS61DDB42M18-250M3L相关器件

型号	品牌	获取价格	描述	数据表
IS61DDB42M18A	ISSI	获取价格	Synchronous pipeline read with late write operation
IS61DDB42M18A-250B4L	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18A-250M3L	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18A-333B4LI	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-250B4	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB42M18C-250B4I	ISSI	获取价格	暂无描述
IS61DDB42M18C-250B4LI	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-250M3L	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-250M3LI	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB42M18C-300B4I	ISSI	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165

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