Datasheet > 存储 > SRAM> IS61DDB24M18-300M3

IS61DDB24M18-300M3

更新时间： 2024-11-18 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器双倍数据速率
页数	文件大小	规格书
25页	601K
描述
72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs

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72 Mb (2M x 3

6 & 4M x 18)

DDR-II (Burst of 2) CIO Synchronous SRAMs

November 2009

• Two echo clocks (CQ and CQ) that are delivered

simultaneously with data.

Features

• 2M x 36 or 4M x 18.

• +1.8V core power supply and 1.5, 1.8V V_DDQ

used with 0.75, 0.9V V_REF

• On-chip delay-locked loop (DLL) for wide data

valid window.

• HSTL input and output levels.

• Common data input/output bus.

• Registered addresses, write and read controls,

byte writes, data in, and data outputs.

• Synchronous pipeline read with self-timed late

write operation.

• Full data coherency.

• Double data rate (DDR-II) interface for read and

• Boundary scan using limited set of JTAG 1149.1

functions.

write input ports.

• Fixed 2-bit burst for read and write operations.

• Clock stop support.

• Byte write capability.

• Fine ball grid array (FBGA) package

- 15mm x 17mm body size

- 1mm pitch

• Two input clocks (K and K) for address and con-

trol registering at rising edges only.

• Two input clocks (C and C) for data output con-

trol.

- 165-ball (11 x 15) array

• Programmable impedance output drivers via 5x

user-supplied precision resistor.

Industrial temperature available upon request.

•

Description

The 72Mb IS61DDB22M36 and

The following are registered on the rising edge of

the K clock:

IS61DDB24M18 are synchronous, high-perfor-

mance CMOS static random access memory

(SRAM) devices. These SRAMs have a common I/O

bus. The rising edge of K clock initiates the

read/write operation, and all internal operations are

self-timed.

•

B te writes

• Data-in for second burst addresses

Byte writes can change with the corresponding data-

in to enable or disable writes on a per-byte basis. An

internal write buffer enables the data-ins to be regis-

tered one cycle later than the write address. The first

data-in burst is clocked with the rising edge of the

next K clock, and the second burst is timed to the

following rising edge of the K clock.

Refer to the Timing Reference Diagram for Truth

Table on page 8 for a description of the basic opera-

tions of these DDR-II (Burst of 2) CIO SRAMs.

The input addresses are registered on all rising

edges of the K clock. The DQ bus operates at

double data rate for reads and writes. The following

are registered internally on the rising edge of the K

clock:

During the burst read operation, at the first burst the

data-outs are updated from output registers off the

second rising edge of the C clock (1.5 cycles later).

At the second burst, the data-outs are updated with

the third rising edge of the corresponding C clock

(see page 9). The K and K clocks are used to time

the data-outs whenever the C and C clocks are tied

high.

• Read and write addresses

• Address load

• Read/write enable

B te writes

• Data-in

The device is operated with a single +1.8V power

supply and is compatible with HSTL I/O interfaces.

Integrated Silicon Solution, Inc.

Rev. B

11/10/09

12 3 4 5 6 7...25

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与IS61DDB24M18-300M3相关器件

型号	品牌	获取价格	描述	数据表
IS61DDB24M18-300M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB24M18A	ISSI	获取价格	Common I/O read and write ports
IS61DDB251236A	ISSI	获取价格	Fixed 2-bit burst for read and write operations
IS61DDB41M18A	ISSI	获取价格	1Mx18, 512Kx36 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M36-250M3	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M36A	ISSI	获取价格	Synchronous pipeline read with late write operation
IS61DDB41M36A-300M3LI	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB41M36C-250M3L	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB41M36C-300M3	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB41M36C-333M3	ISSI	获取价格	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165

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