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IS46R16320E PDF预览

IS46R16320E

更新时间: 2024-11-20 01:20:19
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
33页 1006K
描述
Auto Refresh and Self Refresh Modes

IS46R16320E 数据手册

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IS43R86400E  
IS43/46R16320E, IS43/46R32160E  
ADVANCED INFORMATION  
NOVEMBER 2013  
16Mx32, 32Mx16, 64Mx8  
512Mb DDR SDRAM  
FEATURES  
DEVICE OVERVIEW  
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.2Vꢀ(-5,ꢀ-6)  
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.1Vꢀ(-4)  
•ꢀ SSTL_2ꢀcompatibleꢀI/O  
ISSI’sꢀ512-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ  
transfer using pipeline architecture and two data word  
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ536,870,912-bitꢀmemoryꢀ  
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ128Mbꢀtoꢀ  
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ  
and Write burst accesses to be virtually continuous, with  
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ  
programmableꢀfeaturesꢀofꢀburstꢀlength,ꢀburstꢀsequenceꢀ  
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ  
isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ  
InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ  
ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ  
toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ  
CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ  
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ  
per clock cycle  
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/  
received with data, to be used in capturing data  
at the receiver  
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ  
centre-alignedꢀwithꢀdataꢀforꢀWRITEs  
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)  
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ  
transitions  
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀ  
data and data mask referenced to both edges of  
DQS  
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ  
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.  
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation  
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ  
ADDRESS TABLE  
at both rising and falling edges of data strobe  
Parameter  
16M x 32  
32M x 16  
64M x 8  
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8  
Configuration 4Mꢀxꢀ32ꢀxꢀ4ꢀ  
8Mꢀxꢀ16ꢀxꢀ4ꢀ  
16Mꢀxꢀ8ꢀxꢀ4ꢀ  
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode  
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ  
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes  
•ꢀ AutoꢀPrecharge  
banks  
banks  
banks  
BankꢀAddressꢀ BA0,ꢀBA1  
Pins  
BA0,ꢀBA1  
BA0,ꢀBA1  
Autoprecharge A8/AP  
A10/AP  
A10/AP  
Pins  
OPTIONS  
RowꢀAddress 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)  
•ꢀ Dieꢀrevision:ꢀD  
Column  
Address  
512(A0ꢀ–ꢀA7,ꢀ 1K(A0ꢀ–ꢀA9)  
A9)  
2K(A0ꢀ–ꢀA9,ꢀ  
A11)  
•ꢀ Configuration(s):ꢀ  
ꢀ 16Mx32  
ꢀ 32Mx16  
64Mx8  
RefreshꢀCount  
Com./Ind./A1 8Kꢀ/ꢀ64ms  
A2 8Kꢀ/ꢀ16ms  
8Kꢀ/ꢀ64ms  
8Kꢀ/ꢀ16ms  
8Kꢀ/ꢀ64ms  
8Kꢀ/ꢀ16ms  
•ꢀ Package(s):ꢀ  
ꢀ 144ꢀBallꢀBGAꢀ(x32)  
66-pinꢀTSOP-IIꢀ(x8,ꢀx16)ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)  
•ꢀ Lead-freeꢀpackageꢀavailable  
•ꢀ TemperatureꢀRange:ꢀ  
KEY TIMING PARAMETERS  
Speed Grade  
-4  
-5  
-6  
Units  
x8, x16  
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)  
only  
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)  
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)  
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)  
F
F
F
ckꢀMaxꢀCLꢀ=ꢀ3ꢀ  
ckꢀMaxꢀCLꢀ=ꢀ2.5ꢀ 167ꢀ 167ꢀ  
ckꢀMaxꢀCLꢀ=ꢀ2ꢀ 133ꢀ 133ꢀ  
250ꢀ 200ꢀ  
167ꢀ  
167ꢀ  
133ꢀ  
MHz  
MHz  
MHz  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc.  
1
Rev. 00A  
10/24/13  

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