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IS24C256-2GLI PDF预览

IS24C256-2GLI

更新时间: 2024-09-20 19:24:31
品牌 Logo 应用领域
美国芯成 - ISSI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟双倍数据速率光电二极管内存集成电路
页数 文件大小 规格书
13页 56K
描述
EEPROM, 32KX8, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8

IS24C256-2GLI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.84
最大时钟频率 (fCLK):0.1 MHz数据保留时间-最小值:40
耐久性:100000 Write/Erase CyclesI2C控制字节:1010DDDR
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
内存密度:262144 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):260
电源:2/5 V认证状态:Not Qualified
串行总线类型:I2C最大待机电流:0.000001 A
子类别:EEPROMs最大压摆率:0.003 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40最长写入周期时间 (tWC):10 ms
写保护:HARDWAREBase Number Matches:1

IS24C256-2GLI 数据手册

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®
IS24C256  
ISSI  
256K-bit  
2-WIRE SERIAL CMOS EEPROM  
ADVANCEDINFORMATION  
MARCH2005  
FEATURES  
DESCRIPTION  
• Two-Wire Serial Interface, I2CTM compatible  
–Bi-directional data transfer protocol  
• 400 KHz (2.5V) and 1 MHz (5.0V) compatibility  
• Low Power CMOS Technology  
The IS24C256 is an electrically erasable PROM device  
that uses the standard 2-wire interface for  
communications. The IS24C256 contains a memory  
array of 256K-bits (32,768 x 8), and is further  
subdivided into 512 pages of 64 bytes each for Page-  
Write mode. This EEPROM is offered in wide operating  
voltages of 1.8V to 5.5V (IS24C256-2) and 2.5V to 5.5V  
(IS24C256-3) to be compatible with most application  
voltages. ISSI designed the IS24C256 to be a low-cost  
and low-power 2-wire EEPROM solution. The devices  
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin  
TSSOP.  
–Active Current less than 3 mA (5.0V)  
–Stanby Current less than 6 µA (5.0V)  
–Standby Current less than 2 µA (2.5V)  
• Wide Voltage Operation  
–Vcc = 1.8V to 5.5V for -2 version  
–Vcc = 2.5V to 5.5V for -3 version  
• Hardware Data Protection  
The IS24C256 maintains compatibility with the popular  
2-wire bus protocol, so it is easy to design into  
applications implementing this bus type. The simple  
bus consists of the Serial Clock wire (SCL) and the  
Serial Data wire (SDA). Using the bus, a Master device  
such as a microcontroller is usually connected to one  
or more Slave devices such as the IS24C256. The bit  
stream over the SDA line includes a series of bytes,  
which identifies a particular Slave device, an  
instruction, an address within that Slave device, and a  
series of data, if appropriate. The IS24C256 has a Write  
Protect pin (WP) to allow blocking of any write  
instruction transmitted over the bus.  
–Write Protect Pin  
• Sequential Read Feature  
• Filtered Inputs for Noise Suppression  
• Self time write cycle with auto clear  
–5 ms @ 2.5V  
• Organization:  
–32Kx8 (512 pages of 64 bytes)  
• 64 Byte Page Write Buffer  
• High Reliability  
–Endurance: 100,000 Cycles  
–Data Retention: 40 Years  
• Industrial and Automotive temperature ranges  
• 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP  
packages  
• Lead-free available  
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI  
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device  
specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCEDINFORMATION Rev. 00D  
1
03/11/05  

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