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IS24C256-3ZI PDF预览

IS24C256-3ZI

更新时间： 2024-09-19 22:48:03
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
12页 53K
描述
262,144-bit 2-WIRE SERIAL CMOS EEPROM

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中文翻译

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IS24C256-3ZI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP-14
针数：14Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.92Is Samacsys：N
最大时钟频率 (fCLK)：0.4 MHzJESD-30 代码：R-PDSO-G14
JESD-609代码：e0长度：5 mm
内存密度：262144 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端子数量：14字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX8封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行：SERIAL
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.2 mm串行总线类型：I2C
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
最长写入周期时间 (tWC)：10 msBase Number Matches：1

IS24C256-3ZI 数据手册

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®
IS24C256  
ISSI  
262,144-bit 2-WIRE SERIAL  
CMOS EEPROM  
ADVANCEDINFORMATION  
MARCH 2003  
DESCRIPTION  
The IS24C256 is an electrically erasable PROM device  
that uses the standard 2-wire interface for  
FEATURES  
• Organization:  
communications. The IS24C256 contains a memory  
array of 256K-bits (32,768 x 8), and is further  
subdivided into 512 pages of 64 bytes each for Page-  
Write mode. This EEPROM is offered in wide operating  
voltages of 1.8V to 5.5V (IS24C256-2) and 2.5V to 5.5V  
(IS24C256-3) to be compatible with most application  
voltages. ISSI designed the IS24C256 to be a low-cost  
and low-power 2-wire EEPROM solution. The devices  
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin  
TSSOP.  
– 32K-bit x 8-bit  
• 64-Byte Page Write Buffer  
• Two-Wire Serial Interface  
– Bi-directional data transfer protocol  
• Low Power CMOS Technology  
– Active Current less than 3 mA (5V)  
– Standby Current less than 6 µA (5V)  
– Standby Current less than 2 µA (2.5V)  
• Wide Voltage Operation  
The IS24C256 maintains compatibility with the popular  
2-wire bus protocol, so it is easy to design into  
applications implementing this bus type. The simple  
bus consists of the Serial Clock wire (SCL) and the  
Serial Data wire (SDA). Using the bus, a Master device  
such as a microcontroller is usually connected to one  
or more Slave devices such as the IS24C256. The bit  
stream over the SDA line includes a series of bytes,  
which identifies a particular Slave device, an  
instruction, an address within that Slave device, and a  
series of data, if appropriate. The IS24C256 has a Write  
Protect pin (WP) to allow blocking of any write  
instruction transmitted over the bus.  
– IS24C256-2: Vcc = 1.8V to 5.5V  
– IS24C256-3: Vcc = 2.5V to 5.5V  
• 1 MHz (I2CTM Protocol) Compatibility  
• Hardware Data Protection  
– Write Protect pin  
• Sequential Read Feature  
• Filtered Inputs for Noise Suppression  
• Self time Write cycle with auto clear  
– 5 ms @ 5.0V  
• HighReliability  
– Endurance: 100,000 Cycles  
– Data Retention: 40 Years  
• Commercial and Industrial temperature ranges  
• 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCEDINFORMATION Rev. 00B  
1
03/11/03  
1234567...12

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