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IDT89HPES24N3AZABXG PDF预览

IDT89HPES24N3AZABXG

更新时间: 2024-09-17 14:51:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
30页 553K
描述
Micro Peripheral IC

IDT89HPES24N3AZABXG 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NBase Number Matches:1

IDT89HPES24N3AZABXG 数据手册

 浏览型号IDT89HPES24N3AZABXG的Datasheet PDF文件第2页浏览型号IDT89HPES24N3AZABXG的Datasheet PDF文件第3页浏览型号IDT89HPES24N3AZABXG的Datasheet PDF文件第4页浏览型号IDT89HPES24N3AZABXG的Datasheet PDF文件第5页浏览型号IDT89HPES24N3AZABXG的Datasheet PDF文件第6页浏览型号IDT89HPES24N3AZABXG的Datasheet PDF文件第7页 
89HPES24N3A  
Data Sheet  
Preliminary Information*  
24-Lane 3-Port  
PCI Express® Switch  
Flexible Architecture with Numerous Configuration Options  
Device Overview  
Automatic per port link width negotiation to x8, x4, x2 or x1  
Automatic lane reversal on all ports  
Automatic polarity inversion on all lanes  
The 89HPES24N3A is a member of IDT’s PRECISE™ family of PCI  
Express® switching solutions. The PES24N3A is a 24-lane, 3-port  
peripheral chip that performs PCI Express packet switching with a  
feature set optimized for high performance applications such as servers,  
storage, and communications/networking. It provides connectivity and  
switching functions between a PCI Express upstream port and two  
downstream ports and supports switching between downstream ports.  
Ability to load device configuration from serial EEPROM  
Legacy Support  
PCI compatible INTx emulation  
Bus locking  
Highly Integrated Solution  
Features  
Requires no external components  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/  
10B encoder/decoder (no separate transceivers needed)  
High Performance PCI Express Switch  
Twenty-four 2.5 Gbps PCI Express lanes  
Three switch ports  
Upstream port configurable up to x8  
Downstream ports configurable up to x8  
Low-latency cut-through switch architecture  
Support for Max Payload Size up to 2048 bytes  
One virtual channel  
Reliability, Availability, and Serviceability (RAS) Features  
Supports ECRC and Advanced Error Reporting  
Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
Compatible with Hot-Plug I/O expanders used on PC and  
server motherboards  
Eight traffic classes  
PCI Express Base Specification Revision 1.1 compliant  
Block Diagram  
3-Port Switch Core  
Port  
Arbitration  
Frame Buffer  
Route Table  
Scheduler  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
...  
...  
...  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
24 PCI Express Lanes  
x8 Upstream Port and Two x8 Downstream Ports  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 30  
December 21, 2006  
DSC 6921  
© 2006 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  

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