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IDT89PES12N3BCG PDF预览

IDT89PES12N3BCG

更新时间： 2024-09-17 14:51:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
2页 47K
描述
Micro Peripheral IC

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中文翻译

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IDT89PES12N3BCG 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：NBase Number Matches：1

IDT89PES12N3BCG 数据手册

 浏览型号IDT89PES12N3BCG的Datasheet PDF文件第2页 
PES12N3  
Product Brief  
12 Lane 3-Port PCI Non-Transparent  
PCI Express® Switch  
◆
Highly Integrated Solution  
Device Overview  
– Requires no external components  
– Incorporates on-chip internal memory for packet buffering and  
queueing  
The PES12N3, a 12 lane 3-port PCI Express® switch, is a member  
of IDT’s PRECISE™ family of PCI Express bridging and switching solu-  
tions. The PES12N3 is a peripheral chip that performs PCI Express  
Base switching with a feature set optimized for high performance appli-  
cations such as servers and storage. It provides connectivity and  
switching functions between a PCI Express upstream port and two  
downstream ports or peer-to-peer switching between downstream ports.  
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/  
decoder (no separate transceivers needed)  
Reliability, Availability, and Serviceability (RAS) Features  
– Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
◆
Features  
– Supports ECRC  
◆
High Performance PCI Express Switch  
– Supports PCI Express Native Hot-Plug  
• Compatible with Hot-Plug I/O expanders used on PC moth-  
erboards  
– Three x4 ports with 12 PCI lanes total  
– Delivers 6 GBps (48 Gbps) aggregate switching capacity  
– Low latency cut-through switch architecture  
– Supports 128 and 256 byte maximum payload size  
– Supports one virtual channel  
– Supports Hot-Swap  
◆
Power Management  
– Supports PCI Express Power Management Interface specifica-  
tion, Revision 1.1 (PCI-PM)  
– Unused SerDes are disabled.  
– PCI Express Base specification Revision 1.0a compliant  
Flexible Architecture with Numerous Configuration Options  
◆
– Port arbitration schemes utilizing round robin or weighted  
round robin algorithms  
– Supports automatic per port link with negotiation (x4, x2, or x1)  
– Supports static lane reversal on all ports  
– Supports polarity inversion  
– Supports locked transactions, allowing use with legacy soft-  
ware  
– Ability to load device configuration from serial EEPROM  
– Supports Advanced Configuration and Power Interface Speci-  
fication, Revision 2.0 (ACPI) supporting active link state  
◆
Testability and Debug Features  
– Supports IEEE 1149.6 JTAG  
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator  
– Ability to read and write any internal register via the SMBus  
– Ability to bypass link training and force any link into any mode  
Block Diagram  
3-Port Switch Core  
Port  
Arbitration  
Scheduler  
Route Table  
Frame Buffer  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Data Link Layer  
Multiplexer/Demultiplexer  
Multiplexer/Demultiplexer  
Multiplexer/Demultiplexer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
12 PCI Express Lanes  
One x4 Upstream Port and Two x4 Downstream Ports  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 2  
December 22, 2005  
DSC 6801  
2005 Integrated Device Technology, Inc.  
12

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