Datasheet > IDT89TSF552BL

IDT89TSF552BL

更新时间： 2024-09-17 14:51:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
38页	755K
描述
Telecom IC, CMOS, PBGA1517

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IDT89TSF552BL 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
JESD-30 代码：	S-PBGA-B1517	JESD-609代码：	e0
端子数量：	1517	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA1517,39X39,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	1.8,2.5,3.3 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	表面贴装：	YES
技术：	CMOS	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

IDT89TSF552BL 数据手册

89TSF552

Switch Fabric Data Sheet

Preliminary Information*

is configurable up to OC-192.

Description

◆

Always non-blocking architecture across destination, traffic

type (cell, packet), and class of service (CoS).

The 89TSF5xx is a complete switch fabric, consisting of two chips:

89TSF552 (queuing engine, 10 Gbps).

◆

Supports up to 4 egress subports per switch port.

Carrier class reliability features:

89TSF500 (crossbar and scheduler).

The 89TSF552 typically resides on a line card and the 89TSF500

usually resides on a separate switch card. An 89TSF552 connects with

the 89TSF500 through high-speed serial links.

–

Flexible architecture that allows the 89TSF switch fabric to be

employed in a single switch shelf or in multiple switch shelves.

Automatic link diagnostics that detect faulty link connections.

Both n+m (load-sharing mode) and 1:1 protection (active/

standby mode) on serial links.

–

The 89TSF5xx switch fabric has a modular and scalable architecture

that gives system designers maximum flexibility and performance. This

architecture allows a switch to be implemented either on a single shelf

using an electrical backplane or on multiple shelves connected by

optical transceivers, thus helping system vendors overcome physical

space constraints.

–

Patented error correction scheme to reduce the system bit

error rate by 10⁵.

Line cord redundancy via Redundant Destination Mapping

(RDM) and Queue-Mapped Redundancy (QMR).

Dynamic 89TSF500 rerouting that avoids congested or faulty

89TSF500s.

Zero cell loss during controlled switchover to standby

89TSF500s.

The 89TSF552 supports line card speeds up to OC-192 (full duplex).

It incorporates a 16-bit CSIX-over-LVDS interface to line card devices,

allowing the 89TSF5xx to operate seamlessly with the IDT 89TTM552

traffic manager, or other compatible traffic managers and network

processors.

◆

Advanced diagnostic features including multiple loopback

paths.

In the ingress direction, the 89TSF552 manages a set of virtual

output queues (VOQs), negotiates the routing path through the switch

fabric, and transmits data to an 89TSF500. In the egress direction, the

89TSF552 receives data from an 89TSF500 and transmits the traffic,

through a CSIX-over-LVDS interface, either to IDT’s 89TTM552 traffic

manager or to another device (such as a network processor) on the line

card.

◆

Unicast and multicast traffic with up to 8 classes of service.

Industry-standard CSIX-over-LVDS interface.

Backward compatibility with IDT’s ZSF200 switch fabric.

89TSF552 Features

◆

24 embedded SerDes links per device at 2.5 Gbps per link.

◆

Virtual output queues (VOQs) that buffer data according to

destination, traffic type and class of Service (CoS).

89TSF5xx Features

◆

Guaranteed cell ordering.

◆

Up to 32 switch ports, with 24 Gbps available per switch

External processor interface for status and register

configuration.

port.

◆

Variable length CSIX payload (up to 132 bytes) that supports

◆

Support for n+m (load-sharing) and 1:1 (active/standby)

redundancy modes.

any type of traffic.

◆

Virtual output queues (VOQs) in the ingress direction that

eliminate head-of-line blocking. The 256 unicast VOQs

provide:

–

A maximum of 32 ports with 8 CoS, or

A maximum of 16 ports with 4 subports and 4 CoS.

◆

Spatial multicast support with up to 4K global multicast

labels. Each multicast label can specify from 1 to 32 ports.

Efficient backpressure mechanism that eliminates cell loss

caused by congestion.

◆

In-service scalable architecture.

“Stackable” architecture. Total aggregate bandwidth is

linearly proportional to the number of 89TSF500s. Port rate

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

1 of 38

June 17, 2005

DSC 6799

*Notice: The information in this document is subject to change without notice

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与IDT89TSF552BL相关器件

型号	品牌	获取价格	描述	数据表
IDT89TTM552BL	IDT	获取价格	ATM/SONET/SDH IC, CMOS, PBGA1192
IDT89TTM553BL	IDT	获取价格	Telecom IC
IDT8M464S-65C	IDT	获取价格	SRAM Module, 16KX4, 65ns, CMOS, CDIP22
IDT8M464S-85C	IDT	获取价格	SRAM Module, 16KX4, 85ns, CMOS, CDIP22
IDT8M612S100CB	ETC	获取价格	x16 SRAM Module
IDT8M612S25C	IDT	获取价格	SRAM Module, 32KX16, 25ns, CMOS, CDMA40
IDT8M612S30C	ETC	获取价格	x16 SRAM Module
IDT8M612S35C	ETC	获取价格	x16 SRAM Module
IDT8M612S35CB	IDT	获取价格	SRAM Module, 32KX16, 35ns, CMOS, CDMA40
IDT8M612S40C	IDT	获取价格	SRAM Module, 32KX16, 40ns, CMOS, CDMA40

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