89TTM552
Traffic Manager Data Sheet
Preliminary Information*
The 89TTM552 manages its data storage internally. It has fixed
blocks of memory for storing and forwarding data, and for managing
memory resources according to quality of service parameters. Each
block, or cell, contains up to 64 bytes of data payload from a packet. The
89TTM552 can process up to 35 Mcps/Mpps for both arrivals and depar-
tures. The 89TTM552 and 89TTM553 both operate up to 175 MHz.
Description
The 89TTM55x Traffic Manager chipset consists of a 89TTM552
aggregate-flow device and a 89TTM553 per-flow device. The 89TTM55x
Traffic Manager manages bandwidth resources by shaping traffic to
defined rate profiles and by precisely controlling the allocation of band-
width and acceptance of new traffic during times of network congestion.
The 89TTM55x provides a full suite of configurable algorithms that
support quality of service differentiation for any data protocol, at line
rates of 10 Gbps.
The 89TTM552 connects seamlessly to IDT’s 89TSF family of switch
fabric products. It can also operate seamlessly with network processors
and switch fabrics that use one of its 16-bit LVDS interface protocols.
The 89TTM552 can also directly transmit to third-party framers/PHYs
that have SPI4.2 interfaces.
The 89TTM552, which can operate as a standalone device, is a 10
Gbps simplex device providing the following features:
The 89TTM553 consists of a flow-based available-rate scheduler
with a weighted fair queuing (WFQ) engine and adds support for further
hierarchical scheduling with queues for up to 1M flows. Both devices,
the 89TTM552 and 89TTM553, are used when additional hierarchical
scheduling and a large number of simultaneous flows are required. See
Figure 1 for a functional diagram of the 89TTM55x chipset.
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An aggregate-flow (AFQ) scheduler that can be used for class-
based, virtual pipe, or flow scheduling for up to 4K queues.
A logical port scheduler (1K port queues).
Output queuing for channel-based backpressure from a
framer or fabric (1K OQs).
Supports up to 256 MB external data buffering.
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Sophisticated congestion management features to manage
buffer resources.
89TTM552 Interfaces
The 89TTM552 has a 16-bit LVDS receive interface and a 16-bit
LVDS transmit interface. These two interfaces can be configured inde-
pendently to operate in one of the following 4 modes.
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Spatial multicast labeling for the switch fabric and logical multi-
casting.
Packet segmentation and reassembly across fabric or SPI4.2
channels.
Note: In the following 2 modes, up to 16 channels or output
queues are supported.1
AAL-5 segmentation and reassembly.
The 89TTM552 can be used in standalone mode to handle conges-
tion management and scheduling of traffic where three levels of hier-
archy and 4K queues (AFQs) are sufficient.
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OI Forum SPI-4p2 (System Packet Interface, Level 4, Phase
2). SPI-4p2 (or SPI4.2) is a physical interface standard for the
transfer of data between a network processing device and a
framer. It is anticipated that this mode will be used on the
89TTM552’s interface to a network processor or a framer.
NPF Streaming Interface (NPE-NPE).
It is anticipated that this mode will be used on 89TTM552’s
interface to an NPU.
The 89TTM552 can perform simultaneous scheduling of a large
number of flows, each at an individual rate of fine granularity, and with
many user-configurable features allowing maximum flexibility and
performance. It has congestion management mechanisms that manage
shared traffic buffering resources. If buffer memory approaches its limit
because data arrives at a queue faster than it can depart, the 89TTM552
performs per-queue congestion management. It can also intelligently
discard lower priority traffic as it arrives until memory resources become
available.
Note: In the following 2 modes, up to 1024 channels or output
queues are supported.
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NPF Streaming Interface (NPE-Fabric).
It is anticipated that this mode will be used on 89TTM552’s
interface to a switch fabric.
The 89TTM552 controls traffic forwarding, manages the shared
buffer resources with multi-level thresholding, maintains the various
queues, and generates queue service selections (scheduling for depar-
tures) using bandwidth management algorithms developed by IDT.
Using industry-standard 16-bit LVDS Rx and Tx interfaces, the
89TTM552 receives and transmits data as packets or cells.
CSIX over LVDS.
It is anticipated that this mode will be used to interface to a
switch fabric (including the 89TSF552/89TSF500 fabric).
1.
External logic may be required if using a SPI4.2 channel configuration that is
not a power-of-2. Refer to Operation with Unsupported SPI-4 Channel
Configuration on page 11-6 in Chapter 11 of the 89TTM55x User Manual,
available by contacting IDT.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 36
April 7, 2005
DSC 6796
© 2005 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
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