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IDT74LVCH16543APV

更新时间： 2024-09-16 00:01:43
品牌 Logo 应用领域
艾迪悌 - IDT 输出元件
页数 文件大小 规格书
7页 96K
描述
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD

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中文翻译

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IDT74LVCH16543APV 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP56,.4
针数：56Reach Compliance Code：not_compliant
风险等级：5.51其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：18.415 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：225电源：3.3 V
Prop。Delay @ Nom-Sup：5.4 ns传播延迟（tpd）：7.4 ns
认证状态：Not Qualified座面最大高度：2.794 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
翻译：N/A宽度：7.5 mm
Base Number Matches：1

IDT74LVCH16543APV 数据手册

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3.3V CMOS 16-BIT  
REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS,  
IDT74LVCH16543A  
5 VOLT TOLERANT I/O, BUS-HOLD  
FEATURES:  
DESCRIPTION  
• Typical tSK(o) (Output Skew) < 250ps  
The LVCH16543A 16-bit registered transceiver is built using advanced  
dualmetalCMOStechnology. TheLVCH16543Acanbeusedastwo8-bit  
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or  
LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow. The  
A-to-B enable (CEAB) input must be low in order to enter data from the A  
portortooutput data fromtheBport. LEABcontrolsthelatch function. When  
LEAB is low, the A to B latches are transparent. A subsequent low-to-high  
transitionofLEABputstheAlatchesinthestoragemode. OEABperforms  
outputenablefunctionontheBport. DataflowfromtheBporttotheAport  
issimilarbutrequiresusingCEBA,LEBA, andOEBAinputs. Flow-through  
organization of signal pins simplifies layout. All inputs are designed with  
hysteresis for improved noise margin.  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µ W typ. static)  
• All inputs, outputs, and I/O are 5V tolerant  
• Supports hot insertion  
• Available in SSOP and TSSOP packages  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Reduced system switching noise  
Allpinsofthis16-bitregisteredtransceivercanbedrivenfromeither3.3V  
or 5V devices. This feature allows the use of this device as a translator in  
a mixed 3.3V/5V supply system.  
TheLVCH16543Ahasbeendesignedwitha ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
• Data communication and telecommunication systems  
The LVCH16543A has “bus-hold” which retains the inputs’ last state  
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs  
and eliminates the need for pull-up/down resistors.  
FUNCTIONALBLOCKDIAGRAM  
29  
56  
2OEBA  
1OEBA  
31  
54  
2CEBA  
1CEBA  
30  
55  
2LEBA  
1LEBA  
28  
1
2OEAB  
1OEAB  
26  
3
2CEAB  
1CEAB  
2
27  
2LEAB  
1LEAB  
C1  
C1  
15  
2A1  
5
1A1  
42  
52  
2B1  
1B1  
1D  
1D  
C1  
1D  
C1  
1D  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-4612/3  
1234567

中文翻译

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IDT74LVCH16543APV 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVCH16543ADLR TI

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