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IDT74LVCH16646APA PDF预览

IDT74LVCH16646APA

更新时间: 2024-11-06 11:18:59
品牌 Logo 应用领域
艾迪悌 - IDT 总线收发器输出元件
页数 文件大小 规格书
8页 115K
描述
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS 5 VOLT TOLERANT I/O AND BUS-HOLD

IDT74LVCH16646APA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:not_compliant
风险等级:5.72其他特性:WITH DIRECTION CONTROL
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3.3 VProp。Delay @ Nom-Sup:5.7 ns
传播延迟(tpd):7.9 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20翻译:N/A
触发器类型:POSITIVE EDGE宽度:6.1 mm
Base Number Matches:1

IDT74LVCH16646APA 数据手册

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IDT74LVCH16646A  
3.3V CMOS 16-BIT BUS  
TRANSCEIVER/REGISTER  
WITH 3-STATE OUTPUTS,  
5 VOLT TOLERANT I/O AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• Typical tSK(o) (Output Skew) < 250ps  
The LVCH16646A 16-bit bus transceiver and register is built using  
advanced dual metal CMOS technology. This high-speed, low power  
device is organized as two independent 8-bit D-type transceivers with 3-  
state D-type registers.The controls circuitry is organized for multiplexed  
transmission of data between A bus and B bus either directly or from the  
internalstorageregisters.Each8-bittransceiver/registerfeaturesdirection  
control(DIR),over-ridingOutputEnablecontrol(OE)andSelectlines(SAB  
andSBA)toselecteitherreal-timedataorstoreddata.Separateclockinputs  
areprovidedforAandBportregisters. DataontheAorBdatabus, orboth,  
can be stored in the internal registers by the low-to-high transitions at the  
appropriateclockpins. Flow-throughorganizationofsignalpinssimplifies  
layout. All inputs are designed with hysteresis for improved noise margin.  
Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows  
the use of this device as a translator in a mixed 3.3V/5V supply system.  
TheLVCH16646Ahasbeendesignedwitha ±24mAoutputdriver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µ W typ. static)  
• All inputs, outputs, and I/O are 5V tolerant  
• Supports hot insertion  
• Available in SSOP, TSSOP, and TVSOP packages  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Reduced system switching noise  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
• Data communication and telecommunication systems  
The LVCH16646A has “bus-hold” which retains the inputs’ last state  
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs  
and eliminates the need for pull-up/down resistors.  
FUNCTIONALBLOCKDIAGRAM  
29  
56  
2OE  
1OE  
1
28  
1DIR  
2DIR  
55  
30  
2CLKBA  
1CLKBA  
54  
31  
27  
2SBA  
1SBA  
2
2CLKAB  
1CLKAB  
3
26  
2SAB  
1SAB  
1D  
C1  
1D  
One of Eight Channels  
C1  
One of Eight Channels  
1A1 5  
15  
42  
52  
2A1  
1B1  
2B1  
1D  
C1  
1D  
C1  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 1999  
1
© 1999 Integrated Device Technology, Inc.  
DSC-3787/1  

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