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74LVCH16543ADLRG4 PDF预览

74LVCH16543ADLRG4

更新时间： 2024-11-04 04:47:51
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德州仪器 - TI 输出元件
页数 文件大小 规格书
18页 495K
描述
16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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74LVCH16543ADLRG4 数据手册

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SN74LVCH16543A  
16-BIT REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS317M–NOVEMBER 1993–REVISED MARCH 2005  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
1OEAB  
1LEAB  
1CEAB  
GND  
1OEBA  
1LEBA  
1CEBA  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.4 ns at 3.3 V  
2
3
4
53 GND  
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
5
52  
51  
50  
49  
48  
47  
1A1  
1A2  
1B1  
1B2  
6
•
•
•
Typical VOHV (Output VOH Undershoot) > 2 V  
at VCC = 3.3 V, TA = 25°C  
7
V
CC  
V
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
9
Ioff Supports Partial-Power-Down Mode  
Operation  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
46 GND  
45 1B6  
44 1B7  
43 1B8  
42 2B1  
41 2B2  
40 2B3  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
3.3-V VCC  
)
•
•
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
GND  
2B4  
2B5  
2B6  
39  
38  
37  
36  
35  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
V
CC  
V
CC  
– 1000-V Charged-Device Model (C101)  
2A7  
2A8  
GND  
2CEAB  
2LEAB  
2OEAB  
34 2B7  
33 2B8  
DESCRIPTION/ORDERING INFORMATION  
GND  
32  
31  
30  
29  
This 16-bit registered transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
2CEBA  
2LEBA  
2OEBA  
The SN74LVCH16543A can be used as two 8-bit  
transceivers or one 16-bit transceiver. Separate  
latch-enable (LEAB or LEBA) and output-enable  
(OEAB or OEBA) inputs are provided for each  
register, to permit independent control in either  
direction of data flow.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVCH16543ADL  
TOP-SIDE MARKING  
Tube  
SSOP – DL  
LVCH16543A  
Tape and reel  
Tape and reel  
Tape and reel  
SN74LVCH16543ADLR  
SN74LVCH16543ADGGR  
SN74LVCH16543ADGVR  
SN74LVCH16543AGQLR  
SN74LVCH16543AZQLR  
TSSOP – DGG  
TVSOP – DGV  
VFBGA – GQL  
LVCH16543A  
LDH543A  
–40°C to 85°C  
Tape and reel  
LDH543A  
VFBGA – ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...18

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74LVCH16543ADLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVCH16543ADLR TI

完全替代

 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SN74LVCH16543ADLG4 TI

完全替代

 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SN74LVCH16543ADL TI

完全替代

 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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