74LVCH1T45

更新时间： 2024-09-14 06:31:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
30页	632K
描述
Dual supply translating transceiver; 3-state

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74LVCH1T45 数据手册

74LVC1T45; 74LVCH1T45

Dual supply translating transceiver; 3-state

Rev. 02 — 19 January 2010

Product data sheet

1. General description

The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs

that enables bidirectional level translation. They feature one data input-output port (A and

B), a direction control input (DIR) and dual supply pins (V_CC(A)and V_CC(B)). Both V_CC(A)

and V_CC(B)can be supplied at any voltage between 1.2 V and 5.5 V making the device

suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V,

3.3 V and 5.0 V). Pins A and DIR are referenced to V_CC(A)and pin B is referenced to

_CC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows

transmission from B to A.

The devices are fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when either V_CC(A)or V_CC(B)are at

GND level, both A port and B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid

logic level.

2. Features

Wide supply voltage range:

V_CC(A): 1.2 V to 5.5 V

V_CC(B): 1.2 V to 5.5 V

High noise immunity

Complies with JEDEC standards:

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

ESD protection:

HBM JESD22-A114E Class 3A exceeds 4000 V

CDM JESD22-C101C exceeds 1000 V

Maximum data rates:

420 Mbps (3.3 V to 5.0 V translation)

210 Mbps (translate to 3.3 V))

140 Mbps (translate to 2.5 V)

75 Mbps (translate to 1.8 V)

60 Mbps (translate to 1.5 V)

Suspend mode

12 3 4 5 6 7...30

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