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74LVCH16543APAG PDF预览

74LVCH16543APAG

更新时间: 2024-09-15 01:18:11
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 234K
描述
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER

74LVCH16543APAG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-56针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.82
Samacsys Description:TSSOP 6.1 MM 0.5MM PITCH其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:14 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.4 ns传播延迟(tpd):7.4 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
翻译:N/A宽度:6.1 mm
Base Number Matches:1

74LVCH16543APAG 数据手册

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3.3V CMOS 16-BIT  
REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS,  
IDT74LVCH16543A  
5 VOLT TOLERANT I/O, BUS-HOLD  
FEATURES:  
DESCRIPTION  
• Typical tSK(o) (Output Skew) < 250ps  
The LVCH16543A 16-bit registered transceiver is built using advanced  
dualmetalCMOStechnology. TheLVCH16543Acanbeusedastwo8-bit  
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or  
LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow. The  
A-to-B enable (CEAB) input must be low in order to enter data from the A  
portortooutput data fromtheBport. LEABcontrolsthelatch function. When  
LEAB is low, the A to B latches are transparent. A subsequent low-to-high  
transitionof LEABputstheAlatchesinthestoragemode. OEABperforms  
outputenablefunctionontheB port. Dataflow fromtheB porttotheA port  
issimilarbutrequiresusingCEBA, LEBA, andOEBAinputs. Flow-through  
organization of signal pins simplifies layout. All inputs are designed with  
hysteresis for improved noise margin.  
Allpinsofthis16-bitregisteredtransceivercanbedrivenfromeither3.3V  
or 5V devices. This feature allows the use of this device as a translator in  
a mixed 3.3V/5V supply system.  
TheLVCH16543Ahasbeendesignedwitha ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4μ W typ. static)  
• All inputs, outputs, and I/O are 5V tolerant  
• Supports hot insertion  
• Available in TSSOP package  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Reduced system switching noise  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
• Data communication and telecommunication systems  
The LVCH16543A has “bus-hold” which retains the inputs’ last state  
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs  
and eliminates the need for pull-up/down resistors.  
FUNCTIONALBLOCKDIAGRAM  
29  
56  
2OEBA  
1OEBA  
31  
54  
2CEBA  
1CEBA  
30  
55  
2LEBA  
1LEBA  
28  
1
2OEAB  
1OEAB  
26  
3
2CEAB  
1CEAB  
2
27  
2LEAB  
1LEAB  
C1  
C1  
15  
2A1  
5
1A1  
42  
52  
2B1  
1B1  
1D  
1D  
C1  
1D  
C1  
1D  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2016  
1
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4612/6  

74LVCH16543APAG 替代型号

型号 品牌 替代类型 描述 数据表
74LVCH16543APAG8 IDT

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3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
SN74LVCH16543ADGGR TI

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