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IDT74ALVCH16841PV8 PDF预览

IDT74ALVCH16841PV8

更新时间： 2024-11-23 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 66K
描述
Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56

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IDT74ALVCH16841PV8 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknown风险等级：5.56
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：18.415 mm
逻辑集成电路类型：BUS DRIVER位数：10
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：5.1 ns
认证状态：Not Qualified座面最大高度：2.794 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

IDT74ALVCH16841PV8 数据手册

 浏览型号IDT74ALVCH16841PV8的Datasheet PDF文件第2页浏览型号IDT74ALVCH16841PV8的Datasheet PDF文件第3页浏览型号IDT74ALVCH16841PV8的Datasheet PDF文件第4页浏览型号IDT74ALVCH16841PV8的Datasheet PDF文件第5页浏览型号IDT74ALVCH16841PV8的Datasheet PDF文件第6页 
3.3V CMOS 20-BIT  
IDT74ALVCH16841  
BUS-INTERFACE D-TYPE  
LATCH WITH 3-STATE OUT-  
PUTS AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
This20-bitinterfaceD-typelatchisbuiltusingadvanceddualmetalCMOS  
technology. The ALVCH16841 features 3-state outputs designed specifi-  
cally for driving highly capacitive relatively low-impedance loads. This  
device is particularly suitable for implementing buffer registers, unidirec-  
tional bus drivers, and working registers.  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in SSOP, TSSOP, and TVSOP packages  
The ALVCH16841 can be used as two 10-bit latches or one 20-bit latch.  
The20latchesaretransparentD-typelatches.Thedevicehasnoninverting  
data(D)inputsandprovidestruedataatitsoutputs. Whilethelatch-enable  
(1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch  
follow the D inputs. When LE is taken low, the Q outputs are latched at the  
levels set up at the D inputs.  
A buffered output-enable (1OE or 2OE) input can be used to place the  
outputsofthecorresponding10-bitlatchineitheranormallogicstate(high  
orlowlogiclevels)orahigh-impedancestate. Inthehigh-impedancestate,  
the outputs neither load nor drive the bus lines significantly. OE does not  
affecttheinternaloperationofthelatches. Olddatacanberetainedornew  
data can be entered while the outputs are in the high-impedance state.  
The ALVCH16841 has been designed with a ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Suitable for heavy loads  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
The ALVCH16841 has “bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
FUNCTIONALBLOCKDIAGRAM  
28  
1
2OE  
1OE  
56  
29  
42  
1LE  
2LE  
2D1  
55  
1D1  
1D  
C1  
1D  
C1  
15  
2
2Q1  
1Q1  
Q
Q
TO NINE OTHER CHANNELS  
TO NINE OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 1999  
1
©1999 Integrated Device Technology, Inc.  
DSC-4699/2  
123456

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IDT74ALVCH16843PF8 IDT

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IDT74ALVCH16843PV8 IDT

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IDT74ALVCH16863PA8 IDT

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IDT74ALVCH16863PF ETC

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