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IDT74ALVCH16903PA PDF预览

IDT74ALVCH16903PA

更新时间： 2024-11-26 04:58:31
品牌 Logo 应用领域
艾迪悌 - IDT 总线驱动器输出元件
页数 文件大小 规格书
13页 114K
描述
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD

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中文翻译

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IDT74ALVCH16903PA 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP-56
针数：56Reach Compliance Code：not_compliant
风险等级：5.87其他特性：WITH PARITY CHECKER
控制类型：COMMON CONTROL计数方向：UNIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：12
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240电源：3.3 V
Prop。Delay @ Nom-Sup：3.8 ns传播延迟（tpd）：6.1 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
翻译：N/A触发器类型：POSITIVE EDGE
宽度：6.1 mm

IDT74ALVCH16903PA 数据手册

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3.3V CMOS 12-BIT UNIVERSAL  
IDT74ALVCH16903  
BUS DRIVER WITH PARITY  
CHECKER, DUAL 3-STATE  
OUTPUTS AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
This 12-bit universal bus driver is built using advanced dual metal CMOS  
technology. This device has dual outputs and can operate as a buffer or an  
edge-triggered register. In both modes, parity is checked on APAR, which  
arrivesonecycleafterthedatatowhichitapplies.TheYERRoutput,whichis  
produced one cycle after APAR, is open drain.  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in SSOP and TSSOP packages  
MODE selects one of the two data paths. When MODE is low, the device  
operatesasanedge-triggeredregister.Onthepositivetransitionoftheclock  
(CLK)inputandwhentheclock-enable(CLKEN)inputislow,datasetupatthe  
Ainputsisstoredintheinternalregisters.OnthepositivetransitionofCLKand  
when CLKEN is high, only data setup at the 9A-12A inputs is stored in their  
internalregisters.WhenMODEishigh,thedeviceoperatesasabufferanddata  
attheAinputspassesdirectlytotheoutputs.The11A/YERREN servesadual  
purpose;itactsasanormaldatabitandalsoenablesYERRdatatobeclocked  
intotheYERRoutputregister.  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Suitable for heavy loads  
Whenusedasasingledevice,parityoutputenable(PAROE)mustbetied  
high;whenparityinput/output(PARI/O)islow,evenparityisselectedandwhen  
PARI/Oishigh,oddparityisselected.WhenusedinpairsandPAROEislow,  
theparitysumisoutputonPARI/OforcascadingtothesecondALVCH16903.  
WhenusedinpairsandPAROEishigh, PARI/Oacceptsapartialparitysum  
fromthefirstALVCH16903.  
Abufferedoutput-enable(OE)inputcanbeusedtoplacethe24outputsand  
YERRineitheranormallogicstate(highorlowlogiclevels)orahigh-impedance  
state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebuslines  
significantly. The high-impedance state and increased drive provide the  
capabilitytodrivebuslineswithoutneedforinterfaceorpullupcomponents.  
The ALVCH16903 has been designed with a ±24mA output driver. This  
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed  
performance.  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Description  
Max  
Unit  
V
(2)  
VTERM  
Terminal Voltage with Respect to GND  
–0.5 to +4.6  
(3)  
VTERM  
Terminal Voltage with Respect to GND –0.5 to VCC+0.5  
(Outputs Only)  
V
TSTG  
IOUT  
IIK  
Storage Temperature  
DC Output Current  
–65 to +150  
–50 to +50  
±50  
°C  
mA  
mA  
Continuous Clamp Current,  
VI < 0 or VI > VCC  
IOK  
Continuous Clamp Current, VO < 0  
–50  
mA  
mA  
ICC  
ISS  
Continuous Current through each  
VCC or GND  
±100  
The ALVCH16903 has “bus-hold” which retains the inputs’ last state  
whenevertheinputbusgoestoahigh-impedance.Thispreventsfloatinginputs  
andeliminatestheneedforpull-up/downresistors.  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. VCC terminals.  
3. This value is limited to 4.6V maximum.  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter(1)  
Conditions  
VIN = 0V  
VOUT = 0V  
VIN = 0V  
Typ.  
Max. Unit  
CIN  
Input Capacitance  
Output Capacitance  
I/O Port Capacitance  
5
7
7
7
9
9
pF  
pF  
pF  
COUT  
COUT  
NOTE:  
1. As applicable to the device type.  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-4911/2  
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中文翻译

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