Datasheet > 逻辑 > 总线驱动器/收发器> IDT74ALVCH16901

IDT74ALVCH16901

更新时间： 2024-11-25 21:54:23

品牌	Logo	应用领域
艾迪悌 - IDT		总线收发器
页数	文件大小	规格书
9页	81K
描述
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS / CHECKERS AND BUS-HOLD

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IDT74ALVCH16901 数据手册

IDT74ALVCH16901

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITHPARITY

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 18-BIT

IDT74ALVCH16901

UNIVERSAL BUS TRANSCEIVER

WITH PARITY GENERATORS/

CHECKERS AND BUS-HOLD

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

This 18-bit universal bus transceiver is built using advanced dual metal

CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity

transceiver with registers. The device can operate as a feed-through

transceiver or it can generate/check parity from the two 8-bit data buses in

eitherdirection.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

The ALVCH16901 features independent clock (CLKAB or CLKBA),

latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or

CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select

(ODD/EVEN)inputsandseparateerror-signal(ERRAandERRB)outputs

for checking parity. The direction of data flow is controlled by OEAB and

OEBA.WhenSELislow,theparityfunctionsareenabled. WhenSELishigh,

theparityfunctionsaredisabledandthedeviceactsasan18-bitregistered

transceiver.

The ALVCH16901 has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

The ALVCH16901 has “bus-hold” which retains the inputs’ last state

whenever the input bus goes to a high impedance. This prevents floating

inputs and eliminates the need for pull-up/down resistors.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONALBLOCKDIAGRAM

LEAB

1CLKENAB

2CLKENAB

CLKAB

OEAB

OEBA

1B1-1B8

1A1-1A8

1APAR

18-Bit

Storage

Q^A

B-Port

Parity

Generate

and

Check

A Data

A-Port

Parity

Generate

and

Check

B Data

¹BPAR

1ERRA

2B1-2A8

1ERRB

2A1-2A8

2APAR

2ERRB

²BPAR

2ERRA

18-Bit

Storage

ODD/EVEN

SEL

CLKBA

1CLKENBA

2CLKENBA

LEBA

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JUNE 2000

DSC-4582/1

12 3 4 5 6 7...9

中文翻译

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与IDT74ALVCH16901相关器件

型号	品牌	获取价格	描述	数据表
IDT74ALVCH16901PA	IDT	获取价格	3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS / CHECKERS AND BUS-HOLD
IDT74ALVCH16901PA8	IDT	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO64, T
IDT74ALVCH16901PAG	IDT	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO64, G
IDT74ALVCH16901PAG8	IDT	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO64, G
IDT74ALVCH16903	IDT	获取价格	3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HO
IDT74ALVCH16903PA	IDT	获取价格	3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HO
IDT74ALVCH16903PAG	IDT	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, GREEN, TSSOP-56
IDT74ALVCH16903PAG8	IDT	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, GREEN, TSSOP-56
IDT74ALVCH16903PF	IDT	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TVSOP-56
IDT74ALVCH16903PV	IDT	获取价格	3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HO

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