Datasheet > 逻辑 > 总线驱动器/收发器> IDT74ALVCH16903

IDT74ALVCH16903

更新时间： 2024-11-23 04:58:31

品牌	Logo	应用领域
艾迪悌 - IDT		总线驱动器输出元件
页数	文件大小	规格书
13页	114K
描述
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD

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IDT74ALVCH16903 数据手册

IDT74ALVCH16903

3.3VCMOS12-BITUNIVERSALBUSDRIVERWITHPARITYCHECKER

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 12-BIT UNIVERSAL

IDT74ALVCH16903

BUS DRIVER WITH PARITY

CHECKER, DUAL 3-STATE

OUTPUTS AND BUS-HOLD

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

This 12-bit universal bus driver is built using advanced dual metal CMOS

technology. This device has dual outputs and can operate as a buffer or an

edge-triggered register. In both modes, parity is checked on APAR, which

arrivesonecycleafterthedatatowhichitapplies.TheYERRoutput,whichis

produced one cycle after APAR, is open drain.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in SSOP and TSSOP packages

MODE selects one of the two data paths. When MODE is low, the device

operatesasanedge-triggeredregister.Onthepositivetransitionoftheclock

(CLK)inputandwhentheclock-enable(CLKEN)inputislow,datasetupatthe

Ainputsisstoredintheinternalregisters.OnthepositivetransitionofCLKand

when CLKEN is high, only data setup at the 9A-12A inputs is stored in their

internalregisters.WhenMODEishigh,thedeviceoperatesasabufferanddata

attheAinputspassesdirectlytotheoutputs.The11A/YERREN servesadual

purpose;itactsasanormaldatabitandalsoenablesYERRdatatobeclocked

intotheYERRoutputregister.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

Whenusedasasingledevice,parityoutputenable(PAROE)mustbetied

high;whenparityinput/output(PARI/O)islow,evenparityisselectedandwhen

PARI/Oishigh,oddparityisselected.WhenusedinpairsandPAROEislow,

theparitysumisoutputonPARI/OforcascadingtothesecondALVCH16903.

WhenusedinpairsandPAROEishigh, PARI/Oacceptsapartialparitysum

fromthefirstALVCH16903.

Abufferedoutput-enable(OE)inputcanbeusedtoplacethe24outputsand

YERRineitheranormallogicstate(highorlowlogiclevels)orahigh-impedance

state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebuslines

significantly. The high-impedance state and increased drive provide the

capabilitytodrivebuslineswithoutneedforinterfaceorpullupcomponents.

The ALVCH16903 has been designed with a ±24mA output driver. This

driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed

performance.

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

(Outputs Only)

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

°C

Continuous Clamp Current,

VI < 0 or VI > VCC

IOK

Continuous Clamp Current, VO < 0

–50

ICC

ISS

Continuous Current through each

VCC or GND

±100

The ALVCH16903 has “bus-hold” which retains the inputs’ last state

whenevertheinputbusgoestoahigh-impedance.Thispreventsfloatinginputs

andeliminatestheneedforpull-up/downresistors.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. VCC terminals.

3. This value is limited to 4.6V maximum.

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

COUT

NOTE:

1. As applicable to the device type.

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JANUARY 2004

DSC-4911/2

12 3 4 5 6 7...13

中文翻译

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与IDT74ALVCH16903相关器件

型号	品牌	获取价格	描述	数据表
IDT74ALVCH16903PA	IDT	获取价格	3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HO
IDT74ALVCH16903PAG	IDT	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, GREEN, TSSOP-56
IDT74ALVCH16903PAG8	IDT	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, GREEN, TSSOP-56
IDT74ALVCH16903PF	IDT	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TVSOP-56
IDT74ALVCH16903PV	IDT	获取价格	3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HO
IDT74ALVCH16903PV8	IDT	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, SSOP-56
IDT74ALVCH16952	IDT	获取价格	3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
IDT74ALVCH16952PA	IDT	获取价格	3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
IDT74ALVCH16952PA8	IDT	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0
IDT74ALVCH16952PAG	IDT	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0

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