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IDT70P25L25PF PDF预览

IDT70P25L25PF

更新时间: 2024-11-05 00:01:43
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
23页 294K
描述
HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT, 8/4K x 16 DUAL-PORT STATIC RAM

IDT70P25L25PF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:QFF,针数:100
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:25 nsJESD-30 代码:S-PQFP-F100
JESD-609代码:e0长度:14 mm
内存密度:131072 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:100
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX16
封装主体材料:PLASTIC/EPOXY封装代码:QFF
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT70P25L25PF 数据手册

 浏览型号IDT70P25L25PF的Datasheet PDF文件第2页浏览型号IDT70P25L25PF的Datasheet PDF文件第3页浏览型号IDT70P25L25PF的Datasheet PDF文件第4页浏览型号IDT70P25L25PF的Datasheet PDF文件第5页浏览型号IDT70P25L25PF的Datasheet PDF文件第6页浏览型号IDT70P25L25PF的Datasheet PDF文件第7页 
HIGH-SPEED 1.8V  
8/4K x 18 DUAL-PORT  
8/4K x 16 DUAL-PORT  
STATIC RAM  
ADVANCED  
IDT70P35/34L  
IDT70P25/24L  
Features  
select when cascading more than one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
IDT70P35/34L (IDT70P25/24L)  
– Commercial: 20/25ns (max.)  
Full on-chip hardware support of semaphore signaling  
between ports  
– Industrial: 25ns (max.)  
Low-power operation  
Fully asynchronous operation from either port  
LVTTL-compatible, single 1.8V (±100mV) power supply  
Available in a 100-pin Thin Quad Flatpack (TQFP) package,  
100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin  
0.5mm pitch BGA (fpBGA)  
IDT70P35/34L (IDT70P25/24L)  
Active:30.6mW(typ.)  
Standby: 5.4mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT70P35/34L (IDT70P25/24L) easily expands data bus  
width to 36 bits (32 bits) or more using the Master/Slave  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UBL  
UB  
LB  
CE  
OE  
R
LB  
L
CEL  
R
R
OEL  
,
(5)  
(5)  
(4)  
I/O9R-I/O17R  
I/O9L-I/O17L  
I/O  
Control  
I/O  
Control  
(4)  
I/O0R-I/O8R  
I/O0L-I/O8L  
BUSY (2,3)  
L
(2,3)  
BUSY  
R
(1)  
12L  
(1)  
A
A
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
R/W  
L
L
R
R
L
SEM  
R
SEM  
L
(3)  
(3)  
INTR  
M/S  
INTL  
5683 drw 01  
NOTES:  
1. A12 is a NC for IDT70P34 and IDT70P24.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
4. I/O0x - I/O7x for IDT70P25/24.  
5. I/O8x - I/O15x for IDT70P25/24.  
FEBRUARY 2004  
1
DSC-5683/2  
©2004 IntegratedDeviceTechnology,Inc.  

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