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IDT70P3307S233RMI PDF预览

IDT70P3307S233RMI

更新时间: 2024-11-05 03:56:55
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
20页 883K
描述
1024K/512K x18 SYNCHRONOUS DUAL QDR-II

IDT70P3307S233RMI 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:25 X 25 MM, 2.55 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, BGA-576
针数:576Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.84Is Samacsys:N
最长访问时间:0.45 nsJESD-30 代码:S-PBGA-B576
JESD-609代码:e1长度:25 mm
内存密度:18874368 bit内存集成电路类型:QDR SRAM
内存宽度:18功能数量:1
端子数量:576字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX18封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.55 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:25 mmBase Number Matches:1

IDT70P3307S233RMI 数据手册

 浏览型号IDT70P3307S233RMI的Datasheet PDF文件第2页浏览型号IDT70P3307S233RMI的Datasheet PDF文件第3页浏览型号IDT70P3307S233RMI的Datasheet PDF文件第4页浏览型号IDT70P3307S233RMI的Datasheet PDF文件第5页浏览型号IDT70P3307S233RMI的Datasheet PDF文件第6页浏览型号IDT70P3307S233RMI的Datasheet PDF文件第7页 
PRELIMINARY DATASHEET  
IDT70P3307  
1024K/512K x18  
SYNCHRONOUS  
DUAL QDR-II  
TM  
IDT70P3337  
®
Features  
– Four word transfers per clock cycle per port (four word bursts  
on 2 ports)  
18Mb Density (1024K x 18)  
Port Enable pins (E0,E1) for depth expansion  
Dual Echo Clock Output with DLL-based phase alignment  
High Speed Transceiver Logic inputs that can be scaled to  
receive signals from 1.4V to 1.9V  
– Also available 9Mb Density (512K x 18)  
QDR-II x 18 Burst-of-2 Interface  
– Commercial: 233MHz, 250MHz  
Separate, Independent Read and Write Data Ports  
– Supports concurrent transactions  
Scalable output drivers  
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V  
– Output impedance adjustable from 35 ohms to 70 ohms  
1.8V Core Voltage (VDD)  
Dual Echo Clock Output  
Two-Word Burst on all DPRAM accesses  
DDR (Double Data Rate) Multiplexed Address Bus  
– One Read and One Write request per clock cycle  
DDR (Double Data Rate) Data Buses  
– Four word burst data (Two Read and Two Write) per clock on  
each port  
576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)  
JTAG Interface - IEEE 1149.1 Compliant  
Functional Block Diagram  
VREFL  
VREFR  
E
P[1:0]  
E
R[1:0]  
E
L[1:0]  
LEFT PORT  
DATA  
RIGHT PORT  
DATA  
REGISTER  
AND LOGIC  
REGISTER  
AND LOGIC  
D
0L- D1 7 L  
D
0R-  
D17 R  
WRITE DRIVER  
KR  
KL  
KL  
KL  
KR  
KR  
(1)  
(1)  
ZQL  
ZQR  
Q
0L-  
Q
1 7 L  
Q
0R- Q1 7 R  
1024/512K x 18  
MEMORY  
ARRAY  
CQL, CQL  
CQR, CQR  
K
L
KR  
CR  
CL  
(2)  
A
0R- 18R  
(2)  
A
A
0L- A18L  
C
R
, C  
R
R
C
L
, C  
L
R
R
OR K  
R
, K  
OR K  
L
, KL  
RL  
LEFT PORT  
ADDRESS  
REGISTER  
AND LOGIC  
RIGHT PORT  
ADDRESS  
REGISTER  
AND LOGIC  
WR  
WL  
ADDRESS DECODE  
BW0R- BW1R  
BW0L- BW1 L  
KR  
KL  
KR  
KL  
TCK  
TMS  
TRST  
TDI  
6725 drw01  
JTAG  
VREFR  
VREFL  
TDO  
NOTES:  
1. Input pin to adjust the device outputs to the system data bus impedance.  
2. Address A18 is a INC for IDT70P3337. Disabled input pin (Diode tied to VDD and VSS).  
July 16, 2007  
DSC-6725/1  
©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information  
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale  
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."  

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