Datasheet > IDT70P3519S166BCG8

IDT70P3519S166BCG8

更新时间： 2024-11-07 09:25:35

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	312K
描述
SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT70P3519S166BCG8 数据手册

浏览型号IDT70P3519S166BCG8的Datasheet PDF文件第2页

浏览型号IDT70P3519S166BCG8的Datasheet PDF文件第3页

浏览型号IDT70P3519S166BCG8的Datasheet PDF文件第4页

浏览型号IDT70P3519S166BCG8的Datasheet PDF文件第5页

浏览型号IDT70P3519S166BCG8的Datasheet PDF文件第6页

浏览型号IDT70P3519S166BCG8的Datasheet PDF文件第7页

HIGH-SPEED 1.8V

256/128K x 36

SYNCHRONOUS

PRELIMINARY

IDT70P3519/99

DUAL-PORT STATIC RAM

WITH 3.3V/2.5V/1.8V INTERFACE

Features:

◆

Counter enable and repeat features

◆

True Dual-Port memory cells which allow simultaneous

◆

Interrupt and Collision Detection Flags

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

1.8V (±100mV) power supply for core

LVTTL compatible,1.8V to 3.3V power supply for I/Os and

control signals on each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz

Available in a 256-pin Ball Grid Array (BGA), a 208-pin

Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball

GridArray(fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG is not supported on the 208-

pin PQFP package

access of the same memory location

Low Power

High-speed data access

◆

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)

– Industrial: 3.6ns (166MHz)

Selectable Pipelined or Flow-Through output mode

◆

Dual chip enables allow for depth expansion without

◆

additional logic

◆

Full synchronous operation on both ports

– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

◆

Green parts available, see ordering information

FunctionalBlockDiagram

BE3R

BE3L

BE2L

BE1L

BE0L

BE2R

BE1R

BE0R

FT/PIPE

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

FT/PIPE

1/0

R/WL

R/W

CE0L

CE0R

CE1R

CE1L

B B B

1/0

W W W W W W W W

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d 1c 0c

1b 0b 1a 0a

0a 1a 0b 1b

0c 1c 0d 1d

d c b a

0/1

FT/PIPE

FT/PIPER

a bc d

256/128K x 36

MEMORY

ARRAY

I/O0L - I/O35 L

I/O0R - I/O35R

Din_L

Din_R

CLK

(1)

17R

(1)

17L

Counter/

Address

Reg.

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

ADDR_R

ADDR_L

REPEAT

ADS

CNTEN

TDI

TCK

T MS

T RST

INTERRUPT

CE0

CE1

JTAG

COLLISION

DETECTION

LOGIC

CE1

TDO

R/W

COL _L

INT_L

COL_R

INT_R

(2)

ZZR

ZZL

CONTROL

LOGIC

7144 drw 01

NOTES:

1. Address A17 is a NC for the IDT70P3599.

+. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the

JULY 2008

sleep mode pins themselves (ZZx) are not affected during sleep mode.

DSC 7144/1

12 3 4 5 6 7...28

中文翻译

下载PDF

与IDT70P3519S166BCG8相关器件

型号	品牌	获取价格	描述	数据表
IDT70P3519S166BCGI8	IDT	获取价格	SRAM
IDT70P3519S166BCI	IDT	获取价格	SRAM
IDT70P3519S166BF	IDT	获取价格	SRAM
IDT70P3519S166BF8	IDT	获取价格	SRAM
IDT70P3519S166BFG8	IDT	获取价格	SRAM
IDT70P3519S166BFGI	IDT	获取价格	SRAM
IDT70P3519S166BFGI8	IDT	获取价格	SRAM
IDT70P3519S166BFI	IDT	获取价格	SRAM
IDT70P3519S166BFI8	IDT	获取价格	SRAM
IDT70P3519S166DRG8	IDT	获取价格	SRAM

与IDT70P3519S166BCG8相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT70P3519S166BCG8

IDT70P3519S166BCG8 数据手册

与IDT70P3519S166BCG8相关器件

与IDT70P3519S166BCG8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT70P3519S166BCG8

IDT70P3519S166BCG8 数据手册

与IDT70P3519S166BCG8相关器件

与IDT70P3519S166BCG8相关文章

您还可以找

您在本页遇到什么问题？