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IDT70P34L20PFI

更新时间： 2024-11-05 00:01:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
23页 294K
描述
HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT, 8/4K x 16 DUAL-PORT STATIC RAM

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IDT70P34L20PFI 数据手册

 浏览型号IDT70P34L20PFI的Datasheet PDF文件第2页浏览型号IDT70P34L20PFI的Datasheet PDF文件第3页浏览型号IDT70P34L20PFI的Datasheet PDF文件第4页浏览型号IDT70P34L20PFI的Datasheet PDF文件第5页浏览型号IDT70P34L20PFI的Datasheet PDF文件第6页浏览型号IDT70P34L20PFI的Datasheet PDF文件第7页 
HIGH-SPEED 1.8V  
8/4K x 18 DUAL-PORT  
8/4K x 16 DUAL-PORT  
STATIC RAM  
ADVANCED  
IDT70P35/34L  
IDT70P25/24L  
Features  
◆
select when cascading more than one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
◆
◆
◆
◆
◆
IDT70P35/34L (IDT70P25/24L)  
– Commercial: 20/25ns (max.)  
Full on-chip hardware support of semaphore signaling  
between ports  
– Industrial: 25ns (max.)  
Low-power operation  
◆
◆
◆
◆
Fully asynchronous operation from either port  
LVTTL-compatible, single 1.8V (±100mV) power supply  
Available in a 100-pin Thin Quad Flatpack (TQFP) package,  
100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin  
0.5mm pitch BGA (fpBGA)  
IDT70P35/34L (IDT70P25/24L)  
Active:30.6mW(typ.)  
Standby: 5.4mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT70P35/34L (IDT70P25/24L) easily expands data bus  
width to 36 bits (32 bits) or more using the Master/Slave  
◆
◆
◆
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UBL  
UB  
LB  
CE  
OE  
R
LB  
L
CEL  
R
R
OEL  
,
(5)  
(5)  
(4)  
I/O9R-I/O17R  
I/O9L-I/O17L  
I/O  
Control  
I/O  
Control  
(4)  
I/O0R-I/O8R  
I/O0L-I/O8L  
BUSY (2,3)  
L
(2,3)  
BUSY  
R
(1)  
12L  
(1)  
A
A
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
R/W  
L
L
R
R
L
SEM  
R
SEM  
L
(3)  
(3)  
INTR  
M/S  
INTL  
5683 drw 01  
NOTES:  
1. A12 is a NC for IDT70P34 and IDT70P24.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
4. I/O0x - I/O7x for IDT70P25/24.  
5. I/O8x - I/O15x for IDT70P25/24.  
FEBRUARY 2004  
1
DSC-5683/2  
©2004 IntegratedDeviceTechnology,Inc.  
1234567...23

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