PRELIMINARY DATASHET
IDT70P3537
512K/256K x36
SYNCHRONOUS
DUAL QDR-II
TM
IDT70P3517
®
Features
each port
◆
– Four word transfers each of Read & Write per clock cycle per
port (four word bursts on 2 ports)
Octal Data Rate
Port Enable pins (E0,E1) for depth expansion
Dual Echo Clock Output with DLL-based phase alignment
High Speed Transceiver Logic inputs
18Mb Density (512K x 36)
– Also available 9Mb Density (256K x 36)
◆
◆
◆
◆
◆
◆
QDR-II x 36 Burst-of-2 Interface
– Commercial: 233MHz, 250MHz
Two independent ports
– True Dual-Port Access to common memory
Separate, Independent Read and Write Data Buses on each
Port
◆
– scaled to receive signals from 1.4V to 1.9V
Scalable output drivers
◆
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V
– Output impedance adjustable from 35 ohms to 70 ohms
1.8V Core Voltage (VDD)
576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)
JTAG Interface - IEEE 1149.1 Compliant
– Supports concurrent transactions
◆
◆
Two-Word Burst on all DPRAM accesses
DDR (Double Data Rate) Multiplexed Address Bus
– One Read and One Write request per clock cycle
DDR (Double Data Rate) Data Buses
◆
◆
◆
◆
– Four word burst data (Two Read and Two Write) per clock on
Functional Block Diagram
VREFL
VREFR
E
P[1:0]
ER[1:0]
EL[1:0]
LEFT PORT
DATA
RIGHT PORT
DATA
REGISTER
AND LOGIC
REGISTER
AND LOGIC
D
0L- D35L
D
0R-
D35R
WRITE DRIVER
KR
KL
KL
KL
KR
KR
(1)
(1)
ZQL
ZQR
Q
0L-
Q
3 5L
Q
0R- Q35 R
512/256K x 36
MEMORY
ARRAY
CQL, CQL
CQR, CQR
K
L
KR
CR
CL
(2)
A
0R- 17R
(2)
A
0L- 17L
A
A
C
R
, C
R
C
L
, C
L
RR
OR K
R
, KR
OR K
L
, KL
RL
LEFT PORT
ADDRESS
REGISTER
AND LOGIC
RIGHT PORT
ADDRESS
REGISTER
AND LOGIC
WR
WL
ADDRESS DECODE
BW0R- BW3R
BW0L- BW3L
KR
KL
KR
KL
TCK
TMS
TRST
TDI
5677 drw01
JTAG
VREFR
VREFL
TDO
NOTES:
1. Input pin to adjust the device outputs to the system data bus impedance.
2. Address A17 is a INC for IDT70P3517. Disabled input pin (Diode tied to VDD and VSS).
July 16, 2007
DSC-5677/1
©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."