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IDT70P3307S250RMI PDF预览

IDT70P3307S250RMI

更新时间: 2024-11-05 03:56:55
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
20页 883K
描述
1024K/512K x18 SYNCHRONOUS DUAL QDR-II

IDT70P3307S250RMI 数据手册

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PRELIMINARY DATASHEET  
IDT70P3307  
1024K/512K x18  
SYNCHRONOUS  
DUAL QDR-II  
TM  
IDT70P3337  
®
Features  
– Four word transfers per clock cycle per port (four word bursts  
on 2 ports)  
18Mb Density (1024K x 18)  
Port Enable pins (E0,E1) for depth expansion  
Dual Echo Clock Output with DLL-based phase alignment  
High Speed Transceiver Logic inputs that can be scaled to  
receive signals from 1.4V to 1.9V  
– Also available 9Mb Density (512K x 18)  
QDR-II x 18 Burst-of-2 Interface  
– Commercial: 233MHz, 250MHz  
Separate, Independent Read and Write Data Ports  
– Supports concurrent transactions  
Scalable output drivers  
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V  
– Output impedance adjustable from 35 ohms to 70 ohms  
1.8V Core Voltage (VDD)  
Dual Echo Clock Output  
Two-Word Burst on all DPRAM accesses  
DDR (Double Data Rate) Multiplexed Address Bus  
– One Read and One Write request per clock cycle  
DDR (Double Data Rate) Data Buses  
– Four word burst data (Two Read and Two Write) per clock on  
each port  
576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)  
JTAG Interface - IEEE 1149.1 Compliant  
Functional Block Diagram  
VREFL  
VREFR  
E
P[1:0]  
E
R[1:0]  
E
L[1:0]  
LEFT PORT  
DATA  
RIGHT PORT  
DATA  
REGISTER  
AND LOGIC  
REGISTER  
AND LOGIC  
D
0L- D1 7 L  
D
0R-  
D17 R  
WRITE DRIVER  
KR  
KL  
KL  
KL  
KR  
KR  
(1)  
(1)  
ZQL  
ZQR  
Q
0L-  
Q
1 7 L  
Q
0R- Q1 7 R  
1024/512K x 18  
MEMORY  
ARRAY  
CQL, CQL  
CQR, CQR  
K
L
KR  
CR  
CL  
(2)  
A
0R- 18R  
(2)  
A
A
0L- A18L  
C
R
, C  
R
R
C
L
, C  
L
R
R
OR K  
R
, K  
OR K  
L
, KL  
RL  
LEFT PORT  
ADDRESS  
REGISTER  
AND LOGIC  
RIGHT PORT  
ADDRESS  
REGISTER  
AND LOGIC  
WR  
WL  
ADDRESS DECODE  
BW0R- BW1R  
BW0L- BW1 L  
KR  
KL  
KR  
KL  
TCK  
TMS  
TRST  
TDI  
6725 drw01  
JTAG  
VREFR  
VREFL  
TDO  
NOTES:  
1. Input pin to adjust the device outputs to the system data bus impedance.  
2. Address A18 is a INC for IDT70P3337. Disabled input pin (Diode tied to VDD and VSS).  
July 16, 2007  
DSC-6725/1  
©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information  
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale  
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."  

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