PRELIMINARY
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR
ICS873991-147
GENERAL DESCRIPTION
FEATURES
• Fourteen differential 3.3V LVPECL/ECL outputs
• Selectable differential LVPECL or REF_CLK inputs
The ICS873991-147 is a low voltage, low skew, 3.3V
ICS
LVPECL or ECL Clock Generator and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS873991-147 has
two selectable clock inputs. The PCLK, nPCLK pair
HiPerClockS™
• PCLK, nPCLK can accept the following input levels:
LVPECL, CML, SSTL
can accept an LVPECL input and the REF_CLK pin can accept
a LVCMOS or LVTTL input. This device has a fully integrated
PLL along with frequency configurable outputs. An external
feedback input and output regenerates clocks with “zero de-
lay”.
• REF_CLK accepts the following input levels:
LVCMOS, LVTTL
• Input clock frequency range: 6.25MHz to 125MHz
• Maximum output frequency: 500MHz
• VCO range: 200MHz to 1GHz
The four independent banks of outputs each have their own
output dividers, which allow the device to generate a multitude
of different bank frequency ratios and output-to-input frequency
ratios. The output frequency range is 25MHz to 500MHz and
the input frequency range is 6.25MHz to 125MHz.The PLL_SEL
input can be used to bypass the PLL for test and system debug
purposes. In bypass mode, the input clock is routed around the
PLL and into the internal output dividers.
• Output skew: 70ps (typical)
• Cycle-to-cyle jitter: 35ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 3.135V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -3.135V
The ICS873991-147 also has a SYNC output which can be
used for system synchronization purposes. It monitors Bank A
and Bank C outputs for coincident rising edges and signals a
pulse per the timing diagrams in this data sheet. This feature is
used primarily in applications where Bank A and Bank C are
running at different frequencies, and is particularly useful when
they are running at non-integer multiples of each other.
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Industrial temperature available upon request
PIN ASSIGNMENT
Example Applications:
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
39 38 37 36 35 34 33 32 31 30 29 28 27
nQB3 40
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
26
25
24
23
22
21
20
19
18
17
16
15
14
QC1
QB3 41
nQC1
QC0
VCCO
42
nQA0 43
QA0 44
nQC0
VCCO
QD1
ICS873991-147
52-Lead LQFP
10mm x 10mm x 1.4mm
package body
nQA1 45
QA1 46
nQD1
QD0
nQA2 47
QA2 48
Y package
Top View
nQD0
VCCO
QFB
nQA3 49
QA3 50
SYNC_SEL 51
VCO_SEL 52
nQFB
VCCA
1
2
3
4
5
6
7 8 9 10 11 12 13
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
1
ICS873991AY-147 REV. A AUGUST 10, 2007