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ICS874002AG

更新时间: 2024-09-28 21:55:39
品牌 Logo 应用领域
矽成 - ICSI 衰减器PC
页数 文件大小 规格书
10页 208K
描述
PCI EXPRESS JITTER ATTENUATOR

ICS874002AG 数据手册

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PRELIMINARY  
ICS874002  
Integrated  
Circuit  
Systems, Inc.  
PCI EXPRESS  
J
ITTER  
ATTENUATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS874002 is a high performance Differential- (2) Differential LVDS output pairs  
ICS  
to-LVDS Jitter Attenuator designed for use in PCI  
(1) Differential clock input  
HiPerClockS™  
Express™ systems. In some PCI Express™  
systems, such as those found in desktop PCs,  
the PCI Express™ clocks are generated from a  
CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
low bandwidth, high phase noise PLL frequency synthesizer.  
In these systems, a jitter attenuator may be required to  
attenuate high frequency random and deterministic jitter  
components from the PLL synthesizer and from the system  
board. The ICS874002 has 3 PLL bandwidth modes:  
200KHz, 400KHz, and 800KHz. The 200KHz mode will pro-  
vide maximum jitter attenuation, but with higher PLL tracking  
skew and spread spectrum modulation from the motherboard  
synthesizer may be attenuated. 400KHz provides an  
intermediate bandwidth that can easily track triangular  
spread profiles, while providing good jitter attenuation.  
800KHz bandwidth provides the best tracking skew and will  
pass most spread profiles, but the jitter attenuation will not be  
as good as the lower bandwidth modes. Because some 2.5  
Gb serdes have x20 multipliers while others have than x25  
multipliers, the 874002 can be set for 1:1 mode or 5/4  
multiplication mode (i.e. 100MHz input/125MHz output) using  
the F_SEL pin.  
Output frequency range: 98MHz - 160MHz  
Input frequency range: 98MHz - 128MHz  
VCO range: 490MHz - 640MHz  
Cycle-to-cycle jitter: 50ps (maximum) design target  
3.3V operating supply  
3 bandwidth modes allow the system designer to make jitter  
attenuation/tracking skew design trade-offs  
0°C to 70°C ambient operating temperature  
PLL BANDWIDTH  
The ICS874002 uses ICS 3rd Generation FemtoClockTM  
PLL technology to achieve the lowest possible phase noise.  
The device is packaged in a 20 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express™ add-in cards.  
BW_SEL  
0 = PLL Bandwidth: ~200KHz  
Float = PLL Bandwidth: ~400KHz (Default)  
1 = PLL Bandwidth: ~800KHz  
BLOCK DIAGRAM  
PU  
OE  
PIN ASSIGNMENT  
PD  
nQA0  
VDDO  
QA0  
VDDO  
QA1  
nQA1  
F_SEL  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
2
3
4
5
6
7
8
9
Float  
BW_SEL  
0 = ~200KHz  
Float = ~400KHz  
FB_OUT  
nFB_OUT  
nFB_IN  
FB_IN  
GND  
nCLK  
CLK  
MR  
BW_SEL  
nc  
VDDA  
F_SEL  
QA0  
1 = ~800KHz  
0
÷5  
(default)  
PD  
CLK  
nQA0  
QA1  
1
÷4  
Phase  
Detector  
VCO  
PU  
PD  
490 - 640 MHz  
nCLK  
FB_IN  
OE  
VDD  
10  
nQA1  
ICS874002  
20-LeadTSSOP  
PU  
nFB_IN  
÷5 (fixed)  
6.5mm x 4.4mm x 0.92mm  
package body  
FB_OUT  
nFB_OUT  
G Package  
Top View  
PD  
MR  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
874002AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 19, 2005  
1

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