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ICS874002AGLF PDF预览

ICS874002AGLF

更新时间： 2024-09-29 20:08:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 610K
描述
PLL Based Clock Driver, 874002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20

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ICS874002AGLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.77系列：874002
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：6.5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：20
实输出次数：2最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.04 ns座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm最小 fmax：98 MHz
Base Number Matches：1

ICS874002AGLF 数据手册

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PCI EXPRESS/JITTER ATTENUATOR  
ICS874002  
GENERAL DESCRIPTION  
FEATURES  
• Two differential LVDS output pair  
The ICS874002 is a high performance Differential-  
ICS  
to-LVDS Jitter Attenuator designed for use in PCI  
Express systems. In some PCI Express systems,  
such as those found in desktop PCs, the PCI  
Express clocks are generated from a low  
HiPerClockS™  
• One differential clock input  
• CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
bandwidth, high phase noise PLL frequency synthesizer. In  
these systems, a jitter attenuator may be required to attenuate  
high frequency random and deterministic jitter components  
from the PLL synthesizer and from the system board. The  
ICS874002 has 3 PLL bandwidth modes: 200kHz, 400kHz, and  
800kHz. The 200kHz mode will provide maximum jitter  
attenuation, but with higher PLL tracking skew and spread  
spectrum modulation from the motherboard synthesizer may  
be attenuated. The 400kHz provides an intermediate band-  
width that can easily track triangular spread profiles, while  
providing good jitter attenuation. The 800kHz bandwidth  
provides the best tracking skew and will pass most spread  
profiles, but the jitter attenuation will not be as good as the  
lower bandwidth modes. Because some 2.5Gb serdes have x20  
multipliers while others have than x25 multipliers, the  
ICS874002 can be set for 1:1 mode or 5/4 multiplication mode  
(i.e. 100MHz input/125MHz output) using the F_SEL pin.  
• Output frequency range: 98MHz - 160MHz  
• Input frequency range: 98MHz - 128MHz  
• VCO range: 490MHz - 640MHz  
• Cycle-to-cycle jitter: 35ps (maximum)  
• 3.3V operating supply  
• Three bandwidth modes allow the system designer to make  
jitter attenuation/tracking skew design trade-offs  
• 0°C to 70°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
PLL BANDWIDTH (TYPICAL)  
BW_SEL  
0 = PLL Bandwidth: 200kHz  
Float = PLL Bandwidth: 400kHz (Default)  
1 = PLL Bandwidth: 800kHz  
The ICS874002 uses IDT’s 3rd Generation FemtoClockTM  
PLL technology to achieve the lowest possible phase noise.  
The device is packaged in a 20 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express add-in cards.  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Pullup  
OE  
QA0  
VDDO  
QA1  
nQA1  
nQA0  
VDDO  
FB_OUT  
nFB_OUT  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Pulldown  
F_SEL  
nFB_IN  
FB_IN  
GND  
nCLK  
CLK  
MR  
BW_SEL  
nc  
VDDA  
F_SEL  
VDD  
Float  
BW_SEL  
0 = 200kHz  
Float = 400kHz  
1 = 800kHz  
Output Divider  
0 ÷5 (default)  
1 ÷4  
QA0  
nQA0  
Pulldown  
CLK  
OE  
Phase  
Detector  
VCO  
Pullup  
nCLK  
490 - 640 MHz  
ICS874002  
QA1  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.92mm  
package body  
nQA1  
Pulldown  
Pullup  
FB_IN  
nFB_IN  
G Package  
Top View  
÷5 (fixed)  
FB_OUT  
nFB_OUT  
Pulldown  
MR  
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR  
1
ICS874002AG REV. A DECEMBER 6, 2006  
1234567...15

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