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ICS874002AGT PDF预览

ICS874002AGT

更新时间： 2024-09-29 20:17:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 202K
描述
PLL Based Clock Driver, 874002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20

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ICS874002AGT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20针数：20
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.85Is Samacsys：N
系列：874002输入调节：DIFFERENTIAL
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：6.5 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：20
实输出次数：2最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.04 ns座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：4.4 mm最小 fmax：98 MHz
Base Number Matches：1

ICS874002AGT 数据手册

 浏览型号ICS874002AGT的Datasheet PDF文件第2页浏览型号ICS874002AGT的Datasheet PDF文件第3页浏览型号ICS874002AGT的Datasheet PDF文件第4页浏览型号ICS874002AGT的Datasheet PDF文件第5页浏览型号ICS874002AGT的Datasheet PDF文件第6页浏览型号ICS874002AGT的Datasheet PDF文件第7页 
PRELIMINARY  
ICS874002  
Integrated  
Circuit  
Systems, Inc.  
PCI EXPRESS  
™
J
ITTER  
ATTENUATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS874002 is a high performance Differential- • (2) Differential LVDS output pairs  
ICS  
to-LVDS Jitter Attenuator designed for use in PCI  
• (1) Differential clock input  
HiPerClockS™  
Express™ systems. In some PCI Express™  
systems, such as those found in desktop PCs,  
the PCI Express™ clocks are generated from a  
• CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
low bandwidth, high phase noise PLL frequency synthesizer.  
In these systems, a jitter attenuator may be required to  
attenuate high frequency random and deterministic jitter  
components from the PLL synthesizer and from the system  
board. The ICS874002 has 3 PLL bandwidth modes:  
200KHz, 400KHz, and 800KHz. The 200KHz mode will pro-  
vide maximum jitter attenuation, but with higher PLL tracking  
skew and spread spectrum modulation from the motherboard  
synthesizer may be attenuated. 400KHz provides an  
intermediate bandwidth that can easily track triangular  
spread profiles, while providing good jitter attenuation.  
800KHz bandwidth provides the best tracking skew and will  
pass most spread profiles, but the jitter attenuation will not be  
as good as the lower bandwidth modes. Because some 2.5  
Gb serdes have x20 multipliers while others have than x25  
multipliers, the 874002 can be set for 1:1 mode or 5/4  
multiplication mode (i.e. 100MHz input/125MHz output) using  
the F_SEL pin.  
• Output frequency range: 98MHz - 160MHz  
• Input frequency range: 98MHz - 128MHz  
• VCO range: 490MHz - 640MHz  
• Cycle-to-cycle jitter: 50ps (maximum) design target  
• 3.3V operating supply  
• 3 bandwidth modes allow the system designer to make jitter  
attenuation/tracking skew design trade-offs  
• 0°C to 70°C ambient operating temperature  
PLL BANDWIDTH  
The ICS874002 uses ICS 3rd Generation FemtoClockTM  
PLL technology to achieve the lowest possible phase noise.  
The device is packaged in a 20 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express™ add-in cards.  
BW_SEL  
0 = PLL Bandwidth: ~200KHz  
Float = PLL Bandwidth: ~400KHz (Default)  
1 = PLL Bandwidth: ~800KHz  
BLOCK DIAGRAM  
PU  
OE  
PIN ASSIGNMENT  
PD  
nQA0  
VDDO  
QA0  
VDDO  
QA1  
nQA1  
F_SEL  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
2
3
4
5
6
7
8
9
Float  
BW_SEL  
0 = ~200KHz  
Float = ~400KHz  
FB_OUT  
nFB_OUT  
nFB_IN  
FB_IN  
GND  
nCLK  
CLK  
MR  
BW_SEL  
nc  
VDDA  
F_SEL  
QA0  
1 = ~800KHz  
0
÷5  
(default)  
PD  
CLK  
nQA0  
QA1  
1
÷4  
Phase  
Detector  
VCO  
PU  
PD  
490 - 640 MHz  
nCLK  
FB_IN  
OE  
VDD  
10  
nQA1  
ICS874002  
20-LeadTSSOP  
PU  
nFB_IN  
÷5 (fixed)  
6.5mm x 4.4mm x 0.92mm  
package body  
FB_OUT  
nFB_OUT  
G Package  
Top View  
PD  
MR  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
874002AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 19, 2005  
1
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