ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS874005 is a high performance Diff- • Five differential LVDS output pairs
ICS
HiPerClockS™
erential-to-LVDS Jitter Attenuator designed for
• One differential clock input
use in PCI Express systems. In some PCI
Express systems, such as those found in
desktop PCs, the PCI Express clocks are
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874005 has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated.The 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while
providing good jitter attenuation. The 800kHz bandwidth
provides the best tracking skew and will pass most spread
profiles, but the jitter attenuation will not be as good as the
lower bandwidth modes. Because some 2.5Gb serdes have
x20 multipliers while others have than x25 multipliers, the
874005 can be set for 1:1 mode or 5/4 multiplication mode
(i.e. 100MHz input/125MHz output) using the F_SEL pins.
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V operating supply
• 3 bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PLL BANDWIDTH
The ICS874005 uses ICS 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package,
making it ideal for use in space constrained applications
such as PCI Express add-in cards.
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (Default)
1 = PLL Bandwidth: ~800kHz
PIN ASSIGNMENT
BLOCK DIAGRAM
Pulldown
OEA
nQB2
nQA1
QA1
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
QB2
VDDO
QB1
Pulldown
F_SELA
BW_SEL
QA0
Float
F_SELA
0 = ~200kHz
Float = ~400kHz
VDDO
nQB1
0
1
÷5 (default)
÷4
nQA0
QA1
5
6
7
8
QA0
nQA0
MR
BW_SEL
VDDA
QB0
1 = ~800kHz
nQB0
F_SELB
OEB
Pulldown
Pullup
CLK
Phase
Detector
VCO
nQA1
QB0
9
490 - 640MHz
nCLK
GND
GND
nCLK
10
11
12
F_SELA
VDD
F_SELB
0
1
÷5 (default)
÷4
OEA
CLK
nQB0
QB1
M = ÷5 (fixed)
ICS874005
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
nQB1
QB2
G Package
nQB2
Top View
Pulldown
F_SELB
MR
Pulldown
Pullup
OEB
874005AG
www.icst.com/products/hiperclocks.html
REV.A JANUARY 25, 2006
1