ICS874003
PCI EXPRESS
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS874003 is a high performance Dif-
• Three Differential LVDS output pairs
• One Differential clock input
ICS
ferential-to-LVDS Jitter Attenuator designed for
use in PCI Express systems. In some PCI
Express systems, such as those found in
desktop PCs, the PCI Express clocks are
HiPerClockS™
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874003 has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated.The 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while
providing good jitter attenuation. The 800kHz bandwidth
provides the best tracking skew and will pass most spread
profiles, but the jitter attenuation will not be as good as the
lower bandwidth modes. Because some 2.5Gb serdes have
x20 multipliers while others have than x25 multipliers, the
ICS874003 can be set for 1:1 mode or 5/4 multiplication
mode (i.e. 100MHz input/125MHz output) using the FSEL pins.
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum)
• 3.3V operating supply
• Three bandwidth modes allow the system designer to
make jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PLL BANDWIDTH
The ICS874003 uses ICS 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package,
making it ideal for use in space constrained applications
such as PCI Express add-in cards.
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (default)
1 = PLL Bandwidth: ~800kHz
BLOCK DIAGRAM
Pullup
OEA
PIN ASSIGNMENT
Pulldown
F_SELA
QA1
VDDO
nQA1
VDDO
QB1
1
20
19
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
QA0
QA0
nQA0
MR
Float
BW_SEL
nQB1
F_SELA
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
0
1
÷5 (default)
÷4
F_SELB
OEB
GND
nCLK
CLK
nQA0
QA1
BW_SEL
nc
VDDA
F_SELA
Pulldown
CLK
Phase
Detector
VCO
OEA
VDD
nQA1
10
Pullup
490 - 640MHz
nCLK
ICS874003
20-LeadTSSOP
QB0
F_SELB
0
1
÷5 (default)
÷4
6.5mm x 4.4mm x 0.92mm
package body
nQB0
M = ÷5 (fixed)
G Package
Top View
Pulldown
F_SELB
Pulldown
Pullup
MR
OEB
874003AG
www.icst.com/products/hiperclocks.html
REV.A JANUARY 25, 2006
1