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ICS874003DG-02LF PDF预览

ICS874003DG-02LF

更新时间： 2024-09-29 14:42:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 257K
描述
PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20

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ICS874003DG-02LF 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
Is Samacsys：N系列：874003
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：6.5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：20
实输出次数：3最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.145 ns座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mm最小 fmax：98 MHz
Base Number Matches：1

ICS874003DG-02LF 数据手册

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PRELIMINARY  
PCI EXPRESS™ JITTER ATTENUATOR  
ICS874003D-02  
GENERAL DESCRIPTION  
FEATURES  
The ICS874003D-02 is a high performance Dif-  
• Three Differential LVDS output pairs  
• One Differential clock input  
ICS  
HiPerClockS™  
ferential-to-LVDS Jitter Attenuator designed for use  
in PCI Express systems. In some PCI Express  
systems, such as those found in desktop PCs, the  
PCI Express clocks are generated from a low  
bandwidth, high phase noise PLL frequency  
• CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
• Output frequency range: 98MHz - 320MHz  
• Input frequency range: 98MHz - 128MHz  
• VCO range: 490MHz - 640MHz  
• Cycle-to-cycle jitter: 35ps (maximum)  
• Supports PCI-Express Spread-Spectrum Clocking  
synthesizer. In these systems, a jitter attenuator may be  
required to attenuate high frequency random and deterministic  
jitter components from the PLL synthesizer and from the system  
board. The ICS874003D-02 has a bandwidth of 2.1MHz. The  
2.1MHz provides an intermediate bandwidth that can easily  
track triangular spread profiles, while providing good jitter  
attenuation.  
• The 2.1MHz bandwidth mode allows the system designer to  
make jitter attenuation/tracking skew design trade-offs  
The ICS874003D-02 uses IDT’s 3rd Generation FemtoClockTM  
PLL technology to achive the lowest possible phase noise.  
The device is packaged in a 20 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express add-in cards.  
• 3.3V operating supply  
• 0°C to 70°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
F_SEL[2:0] FUNCTION TABLE  
Inputs  
Outputs  
F_SEL2 F_SEL1 F_SEL0 QA0/nQA0, QA0/nQA0 QB0/nQB0  
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
÷2  
÷5  
÷4  
÷2  
÷2  
÷5  
÷4  
÷4  
÷2  
÷2  
÷2  
÷4  
÷5  
÷4  
÷5  
÷4  
BLOCK DIAGRAM  
Pullup  
OEA  
3
PIN ASSIGNMENT  
Pulldown  
F_SEL2:0  
QA0  
nQA1  
VDDO  
QB0  
QA1  
VDDO  
QA0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
÷5  
÷4  
nQA0  
nQB0  
÷2 (default)  
nQA0  
MR  
F_SEL0  
nc  
VDDA  
F_SEL1  
F_SEL2  
OEB  
GND  
nCLK  
CLK  
QA1  
Pulldown  
Pullup  
CLK  
Phase  
Detector  
VCO  
nQA1  
490 - 640MHz  
nCLK  
3
OEA  
VDD  
ICS874003D-02  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.92mm  
package body  
QB0  
÷5  
÷4  
÷2 (default)  
nQB0  
M = ÷5 (fixed)  
G Package  
Top View  
Pulldown  
Pullup  
MR  
OEB  
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization and/  
or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR  
1
ICS874003DG-02 REV. A AUGUST 30, 2007  
1234567...14

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