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ICS874005-04 PDF预览

ICS874005-04

更新时间： 2024-09-29 05:39:03
品牌 Logo 应用领域
艾迪悌 - IDT 衰减器PC
页数 文件大小 规格书
13页 274K
描述
PCI EXPRESS™ JITTER ATTENUATOR

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中文翻译

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ICS874005-04 数据手册

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PCI EXPRESS™ JITTER ATTENUATOR  
ICS874005-04  
GENERAL DESCRIPTION  
FEATURES  
The ICS874005-04 is a high performance Diff-  
• Five differential LVDS output pairs  
ICS  
erential-to-LVDS Jitter Attenuator designed for use  
in PCI Express systems. In some PCI Express  
systems, such as those found in desktop PCs, the  
PCI Express clocks are generated from a low  
• One differential clock input  
HiPerClockS™  
• Supports 100MHz, 125MHz, and 250MHz Serdes reference  
clocks  
bandwidth, high phase noise PLL frequency synthesizer. In  
these systems, a jitter attenuator may be required to attenuate  
high frequency random and deterministic jitter components from  
the PLL synthesizer and from the system board. The  
ICS874005-04 has 2 PLL bandwidth modes: 300kHz and  
2MHz. The 300kHz mode will provide maximum jitter  
attenuation, but higher PLL tracking skew and spread spectrum  
modulation from the motherboard synthesizer may be  
attenuated. The 2MHz bandwidth provides the best tracking  
skew and will pass most spread profiles. The ICS874005-04  
supports Serdes reference clock frequencies of 100MHz,  
125MHz and 250MHz.  
• CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
• Output frequency range: 98MHz - 320MHz  
• Input frequency range: 98MHz - 128MHz  
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant  
• RMS phase jitter @ 100MHz (1.875MHz – 20MHz):  
0.88ps (typical)  
• VCO range: 490MHz - 640MHz  
• Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4  
• 3.3V operating supply  
The ICS874005-04 uses IDT’s 3rd Generation FemtoClockTM  
PLL technology to achive the lowest possible phase noise.  
The device is packaged in a 24 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express add-in cards.  
• Two bandwidth modes allow the system designer to make  
jitter attenuation/tracking skew design trade-offs  
• 0°C to 70°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
PLL BANDWIDTH  
BW_SEL  
0 = PLL Bandwidth: ~300kHz (default)  
1 = PLL Bandwidth: ~2MHz  
BLOCK DIAGRAM  
Pullup  
OEA  
Pulldown  
Pulldown  
F_SELA  
BW_SEL  
QA0  
PIN ASSIGNMENT  
F_SELA  
0 = ~300kHz  
1 = ~2MHz  
0
1
÷5 (default)  
÷4  
nQA0  
1
2
3
4
nQB2  
nQA1  
QA1  
24  
23  
22  
21  
20  
19  
18  
QB2  
VDDO  
QB1  
nQB1  
QA1  
Pulldown  
Pullup  
CLK  
Phase  
Detector  
VCO  
VDDO  
nQA1  
QB0  
490 - 640MHz  
nCLK  
5
6
7
8
QA0  
nQA0  
MR  
QB0  
nQB0  
F_SELB  
OEB  
F_SELB  
0
1
÷2 (default)  
÷4  
BW_SEL  
VDDA  
17  
16  
15  
14  
13  
nQB0  
QB1  
9
GND  
GND  
nCLK  
CLK  
M = ÷5 (fixed)  
10  
11  
12  
F_SELA  
VDD  
nQB1  
QB2  
OEA  
ICS874005-04  
24-Lead TSSOP  
nQB2  
Pulldown  
F_SELB  
MR  
4.40mm x 7.8mm x 0.925mm package body  
Pulldown  
Pullup  
G Package  
Top View  
OEB  
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR  
1
ICS874005AG-04 REV. A JULY 29, 2008  
1234567...13

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与ICS874005-04相关器件

型号 品牌 获取价格 描述 数据表
ICS874005AG ICSI

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 		PCI EXPRESS TM JITTER ATTENUATOR
ICS874005AG-04LF IDT

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 		PLL Based Clock Driver, 874005 Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.4
ICS874005AG-04LFT IDT

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 		PLL Based Clock Driver, 874005 Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.4
ICS874005AGLF ICSI

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 		PCI EXPRESS TM JITTER ATTENUATOR
ICS874005AGLFT ICSI

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 		PCI EXPRESS TM JITTER ATTENUATOR
ICS874005AGT ICSI

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 		PCI EXPRESS TM JITTER ATTENUATOR
ICS8741004 IDT

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 		DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EX
ICS8741004_1 IDT

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 		DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EX
ICS8741004AG IDT

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 		DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EX
ICS8741004AGI IDT

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 		PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.

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