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ICS874001AGI-02LFT PDF预览

ICS874001AGI-02LFT

更新时间： 2024-09-29 20:01:15
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 760K
描述
PLL Based Clock Driver, 874001 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20

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ICS874001AGI-02LFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.48
系列：874001输入调节：DIFFERENTIAL
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：6.5 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：20实输出次数：1
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
最小 fmax：98 MHzBase Number Matches：1

ICS874001AGI-02LFT 数据手册

 浏览型号ICS874001AGI-02LFT的Datasheet PDF文件第2页浏览型号ICS874001AGI-02LFT的Datasheet PDF文件第3页浏览型号ICS874001AGI-02LFT的Datasheet PDF文件第4页浏览型号ICS874001AGI-02LFT的Datasheet PDF文件第5页浏览型号ICS874001AGI-02LFT的Datasheet PDF文件第6页浏览型号ICS874001AGI-02LFT的Datasheet PDF文件第7页 
PCI Express™ Jitter Attenuator  
ICS874001I-02  
DATA SHEET  
General Description  
Features  
The ICS874001I-02 is a high performance Jitter Attenuator designed  
for use in PCI Express™ systems. In some PCI Express systems,  
such as those found in desktop PCs, the PCI Express clocks are  
generated from a low bandwidth, high phase noise PLL frequency  
synthesizer. In these systems, a jitter attenuator may be required to  
attenuate high frequency random and deterministic jitter  
components from the PLL synthesizer and from the system board.  
The ICS874001I-02 has two different PLL bandwidth modes: 2MHz  
and 3MHz. The 2MHz mode will provide maximum jitter attenuation,  
but with higher PLL tracking skew and spread spectrum modulation  
from the motherboard synthesizer may be attenuated. The 3MHz  
bandwidth provides the best tracking skew and will pass most  
spread profiles, but the jitter attenuation will not be as good as the  
lower bandwidth mode. The 874001I-02 can be set for different  
modes using the F_SELx pins, as shown in Table 3C.  
• One differential LVDS output pair  
• One differential clock input  
• CLK, nCLK can accept the following differential input levels:  
LVPECL, LVDS, LVHSTL, HCSL, SSTL  
• Input frequency range: 98MHz to 128MHz  
• Output frequency range: 98MHz to 640MHz  
• VCO range: 490MHz - 640MHz  
• Cycle-to-cycle jitter: 15ps (maximum), 3.3V  
• RMS period jitter: 3ps (maximum), 3.3V  
• Two bandwidth modes allow the system designer to make jitter  
attenuation/tracking skew design trade-offs  
• Full 3.3V or 2.5V operating supply  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
The ICS874001I-02 uses IDT’s 3RD Generation FemtoClock®  
PLL technology to achieve the lowest possible phase noise. The  
device is packaged in a small 20-pin TSSOP package, making it  
ideal for use in space constrained applications such as PCI Express  
add-in cards.  
PLL Bandwidth Control Table  
BW_SEL  
0 = PLL Bandwidth: 2MHz (default)  
1 = PLL Bandwidth: 3MHz  
Pin Assignment  
PLL_SEL  
1
2
20 nc  
19  
VDDO  
nc  
nc  
nc  
PLL_SEL Control Table  
PLL_SEL  
3
4
18  
17  
Q
nQ  
MR  
BW_SEL  
F_SEL1  
5
6
7
8
9
16 nc  
15  
14  
13  
nc  
GND  
nCLK  
0 = Bypass  
VDDA  
F_SEL0  
1 = VCO (default)  
12 CLK  
11  
OE  
VDD 10  
ICS874001I-02  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.925mm package body  
G Package  
Top View  
ICS874001AGI-02 REVISION A AUGUST 30, 2010  
1
©2010 Integrated Device Technology, Inc.  
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ICS874002AG-02T IDT

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 		PLL Based Clock Driver, 874002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 4.4
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