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ICS873995AYLF PDF预览

ICS873995AYLF

更新时间： 2024-09-29 21:06:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
20页 324K
描述
PLL Based Clock Driver, 873995 Series, 6 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026, TQFP-48

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ICS873995AYLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：7 X 7 MM, 1 MM HEIGHT, LEAD FREE, MS-026, TQFP-48针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84系列：873995
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQFP-G48
JESD-609代码：e3长度：7 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：48
实输出次数：6最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：HTFQFP封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mm最小 fmax：640 MHz
Base Number Matches：1

ICS873995AYLF 数据手册

 浏览型号ICS873995AYLF的Datasheet PDF文件第2页浏览型号ICS873995AYLF的Datasheet PDF文件第3页浏览型号ICS873995AYLF的Datasheet PDF文件第4页浏览型号ICS873995AYLF的Datasheet PDF文件第5页浏览型号ICS873995AYLF的Datasheet PDF文件第6页浏览型号ICS873995AYLF的Datasheet PDF文件第7页 
DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY/MULTIPLIER/DIVIDER  
ICS873995  
GENERAL DESCRIPTION  
FEATURES  
• Six differential 3.3V LVPECL outputs  
The ICS873995 is a Zero Delay/Multiplier/Divider  
ICS  
with hitless input clock switching capability and a  
member of the HiPerClockS™ family of low jitter/  
phase noise devices from IDT. The ICS873995 is  
ideal for use in redundant, fault tolerant clock trees  
• Selectable differential clock inputs  
HiPerClockS™  
• CLKx, nCLKx pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
where low phase noise and low jitter are critical. The device  
receives two differential LVPECL clock signals from which it  
generates 6 LVPECL clock outputs with “zero” delay. The out-  
put divider and feedback divider selections also allow for  
frequency multiplication or division.  
• Input clock frequency range: 49MHz to 213.33MHz  
• Output clock frequency range: 49MHz to 640MHz  
• VCO range: 490MHz to 640MHz  
• External feedback for “zero delay” clock regeneration  
with configurable frequencies  
The ICS873995 Dynamic Clock Switch (DCS) circuit  
continuously monitors both input clock signals. Upon detection  
of a failure (input clock stuck LOW or HIGH for at least 1 period),  
INP_BAD for that clock will be set HIGH. If that clock is the  
primary clock, the DCS will switch to the good secondary clock  
and phase/frequency alignment will occur with minimal output  
phase disturbance.  
• Output skew: 100ps (maximum)  
• RMS phase jitter (1.875MHz - 20MHz): 0.77ps (typical)  
assuming a low phase noise reference clock input  
• 3.3V supply voltage  
• 0°C to 70°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
The low jitter characteristics combined with input clock  
monitoring and automatic switching from bad to good input  
clocks make the ICS873995 an ideal choice for mission criti-  
cal applications that utilize 1G or 10G Ethernet or 1G/4G/10G  
Fibre Channel.  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
3
NA[2:0]  
nMR  
NA[2:0]  
48 47 46 45 44 43 42 41 40 39 38 37  
PLL_SEL  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VCCO_A  
QA0  
PLL_SEL  
nMR  
QA0  
nQA0  
CLK_INDICATOR  
INP1BAD  
INP0BAD  
nINIT  
2
Dynamic Switch  
Logic  
000 ÷1  
001 ÷2  
3
nQA0  
QA1  
nINIT  
010 ÷3  
QA1  
nQA1  
ICS873995  
48-Lead TQFP, E-Pad  
7mm x 7mm x 1.0mm  
package body  
4
011 ÷4  
VEE  
100 ÷5  
SEL_CLK  
5
nQA1  
QA2  
CLK0  
101 ÷6  
QA2  
nQA2  
110 ÷8  
6
nCLK0  
CLK1  
111 ÷10(default)  
0
1
7
nQA2  
VCCO_A  
VCCO_B  
QB0  
8
nCLK1  
EXT_FB  
nEXT_FB  
SEL_CLK  
VEE  
QB0  
nQB0  
MAN_OVERRIDE  
CLK0  
NB[2:0]  
Y Package  
Top View  
9
000 ÷1  
0
1
001 ÷2  
10  
11  
12  
nCLK0  
QB1  
nQB1  
010 ÷3  
Phase  
011 ÷4  
nQB0  
QB1  
Detector  
CLK1  
nCLK1  
100 ÷5  
VCO  
490MHz - 640MHz  
101 ÷6  
QB2  
110 ÷8  
13 14 15 16 17 18 19 20 21 22 23 24  
nQB2  
111 ÷10(default)  
NFB[2:0]  
EXT_FB  
nEXT_FB  
nMR  
nMR  
000 Reserved  
001 Reserved  
010 ÷3  
QFB  
nQFB  
011 ÷4  
100 ÷5  
3
3
NB[2:0]  
101 ÷6  
110 ÷8  
111 ÷10(default)  
NFB[2:0]  
IDT™ / ICS™ LVPECL ZERO DELAY/MULTIPLIER/DIVIDER  
1
ICS873995AY REV. A SEPTEMBER 11, 2008  
1234567...20

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