Datasheet > ICS843002AKI-41LFT

ICS843002AKI-41LFT

更新时间： 2024-11-02 14:51:19

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
24页	331K
描述
Clock Generator, 700MHz, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32

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ICS843002AKI-41LFT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.31
其他特性：	IT ALSO OPERATES AT 3.3V SUPPLY	JESD-30 代码：	S-XQCC-N32
JESD-609代码：	e3	长度：	5 mm
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	700 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	主时钟/晶体标称频率：	19.44 MHz
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压：	2.625 V	最小供电电压：	2.375 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	5 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

ICS843002AKI-41LFT 数据手册

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700MHZ, FEMTOCLOCK^TMVCXO BASED

SONET/SDH JITTER ATTENUATOR

ICS843002I-41

General Description

Features

The ICS843002I-41 is a member of the

• Two Differential LVPECL outputs

HiperClockS™ family of high performance clock

solutions from IDT. The ICS843002I-41 is a PLL

based synchronous clock generator that is

• Selectable CLKx, nCLKx differential input pairs

HiPerClockS™

• CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or

single-ended LVCMOS or LVTTL levels

optimized for SONET/SDH line card applications

where jitter attenuation and frequency translation is needed. The

device contains two internal PLL stages that are cascaded in

series. The first PLL stage uses a VCXO which is optimized to

provide reference clock jitter attenuation and to be jitter tolerant,

and to provide a stable reference clock for the 2nd PLL stage

(typically 19.44MHz). The second PLL stage provides additional

frequency multiplication (x32), and it maintains low output jitter by

using a low phase noise FemtoClock™VCO. PLL multiplication

ratios are selected from internal lookup tables using device input

selection pins. The device performance and the PLL multiplication

ratios are optimized to support non-FEC (non-Forward Error

Correction) SONET/SDH applications with rates up to OC-48

(SONET) or STM-16 (SDH). The VCXO requires the use of an

external, inexpensive pullable crystal. VCXO PLL uses external

passive loop filter components which are used to optimize the PLL

loop bandwidth and damping characteristics for the given

line card application.

• Maximum output frequency: 700MHz

• FemtoClock VCO frequency range: 560MHz - 700MHz

• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal

(12kHz to 20MHz): 0.81ps (typical)

• Full 3.3V or mixed 3.3V core/2.5V output operating supply

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Pin Assignment

The ICS843002I-41 includes two clock input ports. Each one can

accept either a single-ended or differential input. Each input port

also includes an activity detector circuit, which reports input clock

activity through the LOR0 and LOR1 logic output pins. The two

input ports feed an input selection mux. “Hitless switching” is

accomplished through proper filter tuning. Jitter transfer and

wander characteristics are influenced by loop filter tuning, and

phase transient performance is influenced by both loop filter

tuning and alignment error between the two reference clocks.

32 31 30 29 28 27 26 25

LF1

LF0

LOR0

LOR1

ISET

Typical ICS843002I-41 configuration in SONET/SDH Systems:

• VCXO 19.44MHz crystal

V_CC

V_{CCO_LVCMOS}

V_{CCO_LVPECL}

nQB

CLK0

nCLK0

CLK_SEL

QA_SEL2

• Loop bandwidth: 50Hz - 250Hz

V_EE

• Input Reference clock frequency selections:

19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,

622.08MHz

10 11 12 13 14 15 16

• Output clock frequency selections:

19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz,

Hi-Z

ICS843002I-41

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

K Package

Top View

IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

ICS843002AKI-41 REV. B

APRIL 7, 2009

12 3 4 5 6 7...24

中文翻译

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ICS843002AKI-41LFT 替代型号

型号	品牌	替代类型	描述	数据表
843002AKI-41LFT	IDT	功能相似	700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
843002AKI-41LF	IDT	功能相似	700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
843002AKI-41	IDT	功能相似	700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

与ICS843002AKI-41LFT相关器件

型号	品牌	获取价格	描述	数据表
ICS843002AKI-41T	ICSI	获取价格	700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002ALF	ICSI	获取价格	FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY
ICS843002BKI-72LFT	IDT	获取价格	Clock Generator, 122.88MHz, 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-3
ICS843002BY-31	IDT	获取价格	PLL/Frequency Synthesis Circuit
ICS843002BY-31LF	IDT	获取价格	Clock Generator, 700MHz, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD-HD, TQ
ICS843002BY-31LFT	IDT	获取价格	Clock Generator, 700MHz, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD-HD, TQ
ICS843002BY-31T	IDT	获取价格	PLL/Frequency Synthesis Circuit
ICS843002CY31	ICSI	获取价格	700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31	ICSI	获取价格	700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31LF	ICSI	获取价格	700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR

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