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ICS843003AG PDF预览

ICS843003AG

更新时间: 2024-11-01 21:53:55
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矽成 - ICSI /
页数 文件大小 规格书
17页 295K
描述
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS843003AG 数据手册

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ICS843003  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™ C RYSTAL  
-
TO-3.3V LVPECL  
F
REQUENCY  
S
YNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
• Three 3.3V LVPECL outputs on two banks, A Bank with  
one LVPECL pair and B Bank with 2 LVPECL output pairs  
The ICS843003 is a 3 differential output LVPECL  
ICS  
Synthesizer designed to generate Ethernet refer-  
ence clock frequencies and is a member of the  
HiPerClocksfamily of high performance clock  
solutions from ICS. Using a 31.25MHz or  
HiPerClockS™  
• Using a 31.25MHz or 26.041666 crystal, the two output  
banks can be independently set for 625MHz, 312.5MHz,  
156.25MHz or 125MHz  
• Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended input  
• VCO range: 560MHz to 700MHz  
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):  
0.51ps (typical)  
26.041666MHz, 18pF parallel resonant crystal, the following fre-  
quencies can be generated based on the settings of 4 frequency  
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,  
312.5MHz, 156.25MHz, and 125MHz.The 843003 has 2 output  
banks, Bank A with 1 differential LVPECL output pair and Bank  
B with 2 differential LVPECL output pairs.  
• RMS phase noise at 156.25MHz  
Phase noise:  
The two banks have their own dedicated frequency select pins  
and can be independently set for the frequencies mentioned  
above.The ICS843003 uses ICS3rd generation low phase noise  
VCO technology and can achieve 1ps or lower typical rms phase  
jitter, easily meeting Ethernet jitter requirements.The ICS843003  
is packaged in a small 24-pin TSSOP package.  
Offset  
Noise Power  
100Hz ............... -96.8 dBc/Hz  
1KHz ..............-119.1 dBc/Hz  
10KHz ..............-126.4 dBc/Hz  
100KHz ..............-127.0 dBc/Hz  
• Full 3.3V supply mode  
• 0°C to 70°C ambient operating temperature  
• Industrial temperature available upon request  
PIN ASSIGNMENT  
1
2
3
DIV_SELB0  
VCO_SEL  
MR  
24  
23  
22  
DIV_SELB1  
VCCO_B  
QB0  
4
5
6
7
8
9
10  
11  
12  
VCCO_A  
nQB0  
21  
20  
19  
18  
17  
16  
15  
14  
13  
QB1  
nQB1  
XTAL_SEL  
TEST_CLK  
QA0  
nQA0  
OEB  
OEA  
FB_DIV  
XTAL_IN  
XTAL_OUT  
VEE  
VCCA  
VCC  
DIV_SELA1  
DIV_SELA0  
BLOCK DIAGRAM  
ICS843003  
24-LeadTSSOP  
Pullup  
OEA  
4.40mm x 7.8mm x 0.92mm  
DIV_SELA[1:0]  
package body  
Pullup  
VCO_SEL  
G Package  
TopView  
QA0  
0 0 ÷1  
nQA0  
Pulldown  
0 1 ÷2 (default)  
1 0 ÷4  
TEST_CLK  
XTAL_IN  
0
1
0
1
1 1 ÷5  
Phase  
Detector  
VCO  
625MHz  
OSC  
XTAL_OUT  
XTAL_SEL  
Pullup  
QB0  
FB_DIV  
0 0 ÷1  
nQB0  
0 1 ÷2  
0 = ÷20 (default)  
1 = ÷24  
1 0 ÷4 (default)  
1 1 ÷5  
QB1  
Pulldown  
FB_DIV  
DIV_SELB[1:0]  
MR  
nQB1  
Pulldown  
Pullup  
OEB  
843003AG  
www.icst.com/products/hiperclocks.html  
REV. A JULY 27, 2004  
1

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