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ICS843003AGI-01 PDF预览

ICS843003AGI-01

更新时间: 2024-11-02 11:14:39
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
13页 195K
描述
FEMTOCLOCKS-TM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS843003AGI-01 数据手册

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PRELIMINARY  
ICS843003I-01  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL  
FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS843003I-01 is a 3 differential output  
• Three 3.3V LVPECL outputs on two banks, A Bank with  
one LVPECL pair and B Bank with 2 LVPECL output pairs  
ICS  
LVPECL Synthesizer designed to generate  
Ethernet reference clock frequencies and is a  
member of the HiPerClocks™family of high per-  
formance clock solutions from ICS. Using a  
HiPerClockS™  
• Using a 19.53125MHz or 25MHz crystal, the two output  
banks can be independently set for 625MHz, 312.5MHz,  
156.25MHz or 125MHz  
19.53125MHz or 25MHz, 18pF parallel resonant crystal, the  
following frequencies can be generated based on the  
settings of 4 frequency select pins (DIV_SEL[A1:A0],  
DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and  
125MHz. The 843003I-01 has 2 output banks, Bank A with  
1 differential LVPECL output pair and Bank B with 2 dif-  
ferential LVPECL output pairs.  
• Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended input  
• VCO range: 490MHz to 680MHz  
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):  
0.53ps (typical)  
• 3.3V output supply mode  
The two banks have their own dedicated frequency se-  
lect pins and can be independently set for the frequen-  
cies mentioned above. The ICS843003I-01 uses ICS’ 3rd  
generation low phase noise VCO technology and can  
achieve 1ps or lower typical rms phase jitter, easily meet-  
ing Ethernet jitter requirements. The ICS843003I-01 is  
packaged in a small 24-pin TSSOP package.  
• -40°C to 85°C ambient operating temperature  
PIN ASSIGNMENT  
1
2
3
DIV_SELB0  
VCO_SEL  
MR  
24  
23  
22  
DIV_SELB1  
VCCO_B  
QB0  
4
5
6
7
VCCO_A  
nQB0  
21  
20  
19  
18  
17  
16  
15  
14  
13  
QA0  
nQA0  
CLK_ENB  
CLK_ENA  
FB_DIV  
QB1  
nQB1  
XTAL_SEL  
TEST_CLK  
XTAL_IN  
XTAL_OUT  
VEE  
8
9
10  
11  
12  
VCCA  
VCC  
DIV_SELA1  
DIV_SELA0  
BLOCK DIAGRAM  
ICS843003I-01  
24-LeadTSSOP  
4.40mm x 7.8mm x 0.92mm  
Pullup  
CLK_ENA  
package body  
G Package  
TopView  
Pullup  
DIV_SELA[1:0]  
Pullup  
VCO_SEL  
QA0  
0 0 ÷1  
nQA0  
Pulldown  
0 1 ÷2  
TEST_CLK  
XTAL_IN  
0
1
0
1
1 0 ÷3  
1 1 ÷4 (default)  
Phase  
Detector  
VCO  
OSC  
XTAL_OUT  
XTAL_SEL  
Pullup  
QB0  
FB_DIV  
0 0 ÷2  
nQB0  
0 1 ÷4  
0 = ÷25 (default)  
1 = ÷32  
1 0 ÷5  
QB1  
1 1 ÷8 (default)  
Pulldown  
Pullup  
FB_DIV  
DIV_SELB[1:0]  
MR  
nQB1  
Pulldown  
Pullup  
CLK_ENB  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
843003AGI-01  
www.icst.com/products/hiperclocks.html  
REV. A MAY 26, 2005  
1

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