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ICS843004AG-02

更新时间： 2024-11-02 11:14:39
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矽成 - ICSI /
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12页 182K
描述
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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ICS843004AG-02 数据手册

 浏览型号ICS843004AG-02的Datasheet PDF文件第2页浏览型号ICS843004AG-02的Datasheet PDF文件第3页浏览型号ICS843004AG-02的Datasheet PDF文件第4页浏览型号ICS843004AG-02的Datasheet PDF文件第5页浏览型号ICS843004AG-02的Datasheet PDF文件第6页浏览型号ICS843004AG-02的Datasheet PDF文件第7页 
PRELIMINARY  
ICS843004-02  
CRYSTAL-TO-3.3V LVPECL  
FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
• Four 3.3V LVPECL outputs  
The ICS843004-02 is a 4 output LVPECL  
ICS  
Synthesizer optimized to generate clock  
frequencies for a variety of high performance  
• Selectable crystal oscillator interface  
or LVCMOS/LVTTL single-ended input  
HiPerClockS™  
applications and is  
a member of the  
HiPerClocksTM family of high performance clock  
• Crystal input range: 14MHz - 37.78MHz  
• VCO Range: 560MHz - 680MHz  
solutions from ICS.This device can select its input reference  
clock from either a crystal input or a single-ended clock signal  
and can be configured to generate a number of different output  
frequencies via the 3 frequency select pins (F_SEL2:0).The  
ICS843004-02 uses ICS’3rd generation low phase noise VCO  
technology and can achieve 1ps or lower typical rms phase  
jitter.This ensures that it will easily meet clocking requirements  
for high-speed communication protocols such as 10 and 12  
Gigabit Ethernet, 10 Gigbit Fibre Channel, and SONET.This  
device is also suitable for next generation serial I/O  
technologies like serial ATA and SCSI and is conveniently  
packaged in a small 24-pin TSSOP package.  
• Supports the following applications:  
SONET, Ethernet, Serial ATA, SCSI and HDTV  
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):  
0.91ps (typical)  
Offset  
Noise Power  
100Hz ............... -97.1 dBc/Hz  
1kHz ..............-121.6 dBc/Hz  
10kHz ..............-124.9 dBc/Hz  
100kHz ..............-125.1 dBc/Hz  
• Full 3.3V supply mode  
• 0°C to 70°C ambient operating temperature  
FUNCTION TABLE  
Inputs  
M Divider N Divider  
Value  
Value  
F_SEL2 F_SEL1 F_SEL0  
PIN ASSIGNMENT  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
18  
24  
24  
32  
32  
32  
32  
40  
3
4
8
1
2
4
8
8
nQ2  
1
nQ1  
Q1  
24  
23  
22  
21  
2
Q2  
3
VCCO  
Q3  
VCCo  
Q0  
4
nQ3  
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
nQ0  
F_SEL2  
nXTAL_SEL  
TEST_CLK  
MR  
nPLL_SEL  
nc  
nc  
9
VEE  
10  
11  
12  
XTAL_IN  
XTAL_OUT  
F_SEL1  
VCCA  
F_SEL0  
VCC  
ICS843004-02  
24-LeadTSSOP  
4.40mm x 7.8mm x 0.92mm  
BLOCK DIAGRAM  
Pulldown  
nPLL_SEL  
package body  
G Package  
Top View  
N
Q0  
÷1  
÷2  
÷3  
XTAL_IN  
OSC  
nQ0  
0
1
0
1
Q1  
XTAL_OUT  
÷4 (default)  
÷8  
nQ1  
Pulldown  
Phase  
Detector  
TEST_CLK  
VCO  
Q2  
Pulldown  
nXTAL_SEL  
M
nQ2  
÷18  
÷24  
÷32 (default)  
÷40  
Q3  
nQ3  
Pulldown  
MR  
3
F_SEL0:2  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
843004AG-02  
www.icst.com/products/hiperclocks.html  
REV. A JULY 20, 2005  
1
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