Datasheet > ICS843002CY-31

ICS843002CY-31

更新时间： 2024-11-02 11:14:39

品牌	Logo	应用领域
矽成 - ICSI		晶体转换器外围集成电路石英晶振压控振荡器衰减器时钟
页数	文件大小	规格书
27页	271K
描述
700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR

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ICS843002CY-31 数据手册

PRELIMINARY

ICS843002-31

Integrated

Circuit

Systems, Inc.

700MHZ FEMTOCLOCKS™VCXO BASED

FREQUENCY TRANSLATOR AND JITTER ATTENUATOR

GENERAL DESCRIPTION

FEATURES

The ICS843002-31 is a member of the • Outputs:

ICS

HiPerClockS™

HiperClockS™ family of high performance clock

• Two high frequency differential LVPECL outputs

Output frequency: up to 700MHz

solutions from ICS. This monolithic device is a

high-performance, PLL-based synchronous

clock generator and jitter attenuation circuit.The

• One LVCMOS/LVTTL VCXO PLL output with output

enable

ICS843002-31 contains two clock multiplication stages that

are cascaded in series.The first stage is a VCXO-based PLL

that is optimized to provide reference clock jitter attenuation,

to be jitter tolerant, and to provide a stable reference clock

for the second multiplication stage. The second stage is the

proprietary ICS FemtoClock™circuit which is a high-frequency,

sub-picosecond clock multiplier.

• One Reference clock output with output enable

• One LOCK detect output

• Input mux supports 3 selectable inputs: one differential

input pair and two LVCMOS/LVTTL input clocks

• 13-bitVCXO PLL feedback and reference dividers provide

wide range of frequency translation ratio options

The VCXO PLL has an on-chip VCXO circuit that uses an • FemtoClock frequency multiplier supports rate of:

external, inexpensive pullable crystal in the 17.5 to 25MHz

range. The PLL includes 13 bit reference and feedback

dividers supporting complex PLL multiplication ratios and

input reference clock rates as low as 2.3kHz. External loop

filter components are used (two resistors and two capacitors)

to achieve the low loop bandwidth needed for jitter atten-

uation of a recovered data clock.

560MHz - 700MHz

• ‘Lock Detect’ output reports lock status of VCXO PLL

• VCXO PLL circuit provides jitter attenuation with

loop bandwidth of 250Hz and below (user adjustable)

• RMS phase jitter, random at 12kHz to 20MHz:

<1ps (design target)

• 3.3V supply voltage

The FemtoClock circuit can multiply the VCXO crystal

frequency by a factor of 28 or 32 (selectable) and provide a

clock output of up to 700MHz.

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

• Available in both standard and lead-free RoHS-compliant

packages

Clock Input/Output Configuration:

• Clock Inputs - one differential pair, two singled ended

(mux selected)

• Differential input pair can support LVPECL, LVDS,

LVHSTL, SSTL, HCSL or single-ended LVCMOS

or LVTTL levels

PIN ASSIGNMENT

• Singled ended inputs can support LVCMOS or

LVTTL levels

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

• Clock Outputs, FemtoClockS two LVPECL pairs

(selectable output dividers)

VEE

LF1

LF0

REF_CLK

VCLK

LOCK

V^CCO_CMOS

nQB

• Clock Output, VCXO – one single ended output

(at VCXO crystal frequency)

ISET

V^EE

NV1

• Clock Output, other – VCXO reference clock

NV0

ICS843002-31

64-LeadTQFP, EPAD

10mm x 10mm x 1.0mm

package body

V^CC

V^EE

Example Applications:

nQA

CLK0

nCLK0

OE_REF

CLK1

V^CC

• SONET/SDH line card clock generator (up to 622.08MHz

for OC-48) using 8kHz frame clock as input reference

Y package

TopView

V^CCO_PECL

• Jitter attenuation of a recovered communications clock

NPB0

NPB1

NPB2

V^CCA

• Complex-ratio clock frequency translation between

various communication protocols, such as:

• For telecom, OC-12 to E3 rate conversion, 622.08MHz

to 34.368MHz, PLL ratio of 179/32

SEL1

SEL0

CLK2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

• For digital video, ITU-R601 to SMPTE 252M/59.94,

27MHz to 74.17582MHz, PLL ratio of 250/91

The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

843002CY-31

www.icst.com/products/hiperclocks.html

REV.B NOVEMBER 22, 2005

12 3 4 5 6 7...27

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与ICS843002CY-31相关器件

型号	品牌	获取价格	描述	数据表
ICS843002CY-31LF	ICSI	获取价格	700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31LFT	ICSI	获取价格	700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31T	ICSI	获取价格	700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002I	ICSI	获取价格	FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002I-01	ICSI	获取价格	FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002I-40	ICSI	获取价格	175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002I-40	IDT	获取价格	175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002I-41	ICSI	获取价格	700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002I-41	IDT	获取价格	700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002I-72	IDT	获取价格	FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR

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