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HYMD564726BP8J-D43 PDF预览

HYMD564726BP8J-D43

更新时间: 2024-11-18 05:38:47
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
30页 381K
描述
1184pin Unbufferd DDR SDRAM DIMMs

HYMD564726BP8J-D43 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM184
针数:184Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:SINGLE BANK PAGE BURST
最长访问时间:0.7 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N184JESD-609代码:e6
内存密度:4831838208 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:184
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM184
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:2.6 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.09 A
子类别:Other Memory ICs最大压摆率:4.86 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):2.6 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Bismuth (Sn/Bi)端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20Base Number Matches:1

HYMD564726BP8J-D43 数据手册

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184pin Unbuffered DDR SDRAM DIMMs based on 512Mb B ver.  
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 400mil  
TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based unbuffered DIMM series provide  
a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange  
and addition.  
FEATURES  
JEDEC Standard 184-pin dual in-line memory module  
(DIMM)  
Programmable Burst Length 2 / 4 / 8 with both  
sequential and interleave mode  
Two ranks 128M x 72, 128M x 64 and One rank 64M  
x 72, 64M x 64, 32M x 64 organization  
Edge-aligned DQS with data outs and Center-aligned  
DQS with data inputs  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
2.6V ± 0.1V VDD and VDDQ Power supply for  
DDR400, 2.5V ± 0.2V for DDR333 and below  
All inputs and outputs are compatible with SSTL_2  
interface  
Serial Presence Detect (SPD) with EEPROM  
Built with 512Mb DDR SDRAMs in 400 mil TSOP II  
packages  
Fully differential clock operations (CK & /CK) with  
133/166/200MHz  
Lead-free product listed for each configuration  
(RoHS compliant)  
DLL aligns DQ and DQS transition with CK transition  
Programmable CAS Latency: DDR266(2, 2.5 clock),  
DDR333(2.5 clock), DDR400(3 clock)  
ADDRESS TABLE  
# of  
DRAMs  
Refresh  
# of row/bank/column Address  
Method  
Organization  
Ranks  
SDRAMs  
256MB  
512MB  
512MB  
1GB  
32M x 64  
64M x 64  
64M x 72  
128M x 64  
128M x 72  
1
1
1
2
2
32Mb x 16  
64Mb x 8  
64Mb x 8  
128Mb x 8  
128Mb x 8  
4
8
13(A0~A12)/2(BA0,BA1)/10(A0~A9)  
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)  
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)  
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)  
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)  
8K / 64ms  
8K / 64ms  
8K / 64ms  
8K / 64ms  
8K / 64ms  
9
16  
18  
1GB  
PERFORMANCE RANGE  
-D431  
Part-Number Suffix  
Speed Bin  
-J  
DDR333  
2.5-3-3  
-
-H  
DDR266B  
2.5-3-3  
-
Unit  
-
DDR400B  
3-3-3  
200  
CL - tRCD- tRP  
CL=3  
CK  
MHz  
MHz  
MHz  
Max Clock  
CL=2.5  
166  
166  
133  
Frequency  
CL=2  
133  
133  
133  
Note:  
1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 1.1 / May. 2005  
1

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