Datasheet > 存储 > DRAM> HYMD564G726AL8-L

HYMD564G726AL8-L

更新时间： 2024-11-18 05:38:51

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器双倍数据速率
页数	文件大小	规格书
16页	261K
描述
Registered DDR SDRAM DIMM

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HYMD564G726AL8-L 数据手册

64Mx72 bits

Registered DDR SDRAM DIMM

HYMD564G726A(L)8-M/K/H/L

DESCRIPTION

Preliminary

Hynix HYMD564G726A(L)8-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line

Memory Modules(DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD564G726A(L)8-M/

K/H/L series consists of nine 64Mx8 DDR SDRAM in 400mil TSOPII packages on a 184pin glass-epoxy substrate.

Hynix HYMD564G726A(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of

industry stanard. It is suitable for easy interchange and addition.

Hynix HYMD564G726A(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs

are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-

ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.

All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD564G726A(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function

is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden-

tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

512MB (64M x 72) Registered DDR DIMM based on

64Mx8 DDR SDRAM

•

Fully differential clock operations (CK & /CK) with

125MHz/133MHz

•

JEDEC Standard 184-pin dual in-line memory mod-

ule (DIMM)

•

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•

Error Check Correction (ECC) Capability

Registered inputs with one-clock delay

•

tRAS Lock-out function supported

Phase-lock loop (PLL) clock driver to reduce loading

2.5V +/- 0.2V VDD and VDDQ Power supply

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

All inputs and outputs are compatible with SSTL_2

interface

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Factor

HYMD564G726A(L)8-M

HYMD564G726A(L)8-K

HYMD564G726A(L)8-H

HYMD564G726A(L)8-L

133MHz (*DDR266 2-2-2)

133MHz (*DDR266A)

133MHz (*DDR266B)

125MHz (*DDR200)

VDD=2.5V

VDDQ=2.5V

184pin Registered DIMM

5.25 x 1.7 x 0.15 inch

SSTL_2

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/Jan. 2003

12 3 4 5 6 7...16

中文翻译

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与HYMD564G726AL8-L相关器件

型号	品牌	获取价格	描述	数据表
HYMD564G726AL8-M	HYNIX	获取价格	Registered DDR SDRAM DIMM
HYMD564G726AL8M-H	HYNIX	获取价格	Low Profile Registered DDR SDRAM DIMM
HYMD564G726AL8M-K	HYNIX	获取价格	Low Profile Registered DDR SDRAM DIMM
HYMD564G726AL8M-L	HYNIX	获取价格	Low Profile Registered DDR SDRAM DIMM
HYMD564G726AL8M-M	HYNIX	获取价格	Low Profile Registered DDR SDRAM DIMM
HYMD564G726BF8N-D43	HYNIX	获取价格	184pin Registered DDR SDRAM DIMMs
HYMD564G726BF8N-J	HYNIX	获取价格	184pin Registered DDR SDRAM DIMMs
HYMD564G726BFP8N-D43	HYNIX	获取价格	184pin Registered DDR SDRAM DIMMs
HYMD564G726BFP8N-J	HYNIX	获取价格	184pin Registered DDR SDRAM DIMMs
HYMD564G726CFP8N-D43	HYNIX	获取价格	184pin Registered DDR SDRAM DIMMs

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