Datasheet > HYMD564M6466

HYMD564M6466

更新时间： 2024-11-17 23:57:31

品牌	Logo	应用领域
其他 - ETC		动态存储器双倍数据速率
页数	文件大小	规格书
16页	264K
描述
64Mx64\|2.5V\|K/H/L\|x8\|DDR SDRAM - SO DIMM 512MB

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HYMD564M6466 数据手册

64Mx64 bits

Unbuffered DDR SO-DIMM

HYMD564M646(L)6-K/H/L

Preliminary

DESCRIPTION

Hynix HYMD564M646(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline

Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix

HYMD564M646(L)6-K/H/L series consists of eight 32Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin

glass-epoxy substrate. Hynix HYMD564M646(L)6-K/H/L series provide a high performance 8-byte interface in

67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD564M646(L)6-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper-

ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are

latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising

and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All

input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD564M646(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

512MB (64M x 64) Unbuffered DDR SO-DIMM

based on 32Mx16 DDR SDRAM

both rising and falling edges of the clock

•

Data inputs on DQS centers when write (centered

DQ)

•

JEDEC Standard 200-pin small outline dual in-line

memory module (SO-DIMM)

Data strobes synchronized with output data for read

and input data for write

•

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2

interface

•

Programmable CAS Latency 1.5 / 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz

•

tRAS Lock-out function supported

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

•

Data(DQ), Data strobes and Write masks latched on

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Pactor

HYMD564M646(L)6-K

HYMD564M646(L)6-H

HYMD564M646(L)6-L

133MHz (*DDR266A)

133MHz (*DDR266B)

125MHz (*DDR200)

VDD=2.5V

VDDQ=2.5V

200pin Unbuffered SO-DIMM

67.6mm x 31.75mm x 3.8mm

SSTL_2

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/May. 02

12 3 4 5 6 7...16

中文翻译

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与HYMD564M6466相关器件

型号	品牌	获取价格	描述	数据表
HYMD564M6466-L	HYNIX	获取价格	DDR DRAM Module, 64MX64, 0.8ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200
HYMD564M6468	ETC	获取价格	64Mx64\|2.5V\|K/H/L\|x8\|DDR SDRAM - SO DIMM 512MB
HYMD564M6468-H	HYNIX	获取价格	DDR DRAM Module, 64MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200
HYMD564M6468-K	HYNIX	获取价格	DDR DRAM Module, 64MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200
HYMD564M646A6-D4	HYNIX	获取价格	Unbuffered DDR SO-DIMM
HYMD564M646A6-D43	HYNIX	获取价格	Unbuffered DDR SO-DIMM
HYMD564M646A6-H	HYNIX	获取价格	Unbuffered DDR SO-DIMM
HYMD564M646A6-J	HYNIX	获取价格	Unbuffered DDR SO-DIMM
HYMD564M646A6-K	HYNIX	获取价格	Unbuffered DDR SO-DIMM
HYMD564M646A8-H	HYNIX	获取价格	Unbuffered DDR SO-DIMM

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