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HYB18L256160BCX-7.5 PDF预览

HYB18L256160BCX-7.5

更新时间: 2024-01-13 13:12:18
品牌 Logo 应用领域
奇梦达 - QIMONDA 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
48页 1590K
描述
DRAMs for Mobile Applications 256-Mbit Mobile-RAM

HYB18L256160BCX-7.5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA54,9X9,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.24
风险等级:5.83访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PBGA-B54
长度:12 mm内存密度:268435456 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA54,9X9,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH电源:1.8 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.00001 A
子类别:DRAMs最大压摆率:0.045 mA
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:8 mm
Base Number Matches:1

HYB18L256160BCX-7.5 数据手册

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HY[B/E]18L256160B[C/F]X-7.5  
256-Mbit Mobile-RAM  
Functional Description  
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the  
block.  
2.2.1.2  
Burst Type  
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the  
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the  
burst type and the starting column address, as shown in Table 5.  
2.2.1.3  
Read Latency  
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and  
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.  
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock  
edge n + m (for details please refer to the READ command description).  
2.2.1.4  
Write Burst Mode  
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write  
accesses consist of single data elements only.  
2.2.1.5  
Extended Mode Register  
The Extended Mode Register controls additional low power features of the device. These include the Partial Array  
Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive  
strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE  
REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed  
again or the device loses power.  
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified  
time before initiating any subsequent operation. Violating either of these requirements result in unspecified  
operation.  
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.  
EMR  
Extended Mode Register  
(BA[1:0] = 10B)  
BA1  
BA0  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
1
0
0
0
0
0
0
0
DS  
(TCSR)  
PASR  
Field Bits Type Description  
DS  
[6:5]  
w
Selectable Drive Strength  
00 Full Drive Strength  
01 Half Drive Strength (default)  
Note:All other bit combinations are RESERVED.  
TCSR [4:3]  
w
Temperature Compensated Self Refresh  
XX Superseded by on-chip temperature sensor (see text)  
Data Sheet  
10  
Rev. 1.11, 2007-01  
07142005-CR47-RB2E  

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