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HY5DU281622T-K

更新时间： 2024-09-16 21:03:59
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器双倍数据速率光电二极管内存集成电路
页数 文件大小 规格书
10页 85K
描述
DDR DRAM, 8MX16, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66

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HY5DU281622T-K 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2, TSSOP66,.46
针数：66Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.88访问模式：FOUR BANK PAGE BURST
最长访问时间：0.75 ns其他特性：AUTO/SELF REFRESH
最大时钟频率 (fCLK)：143 MHzI/O 类型：COMMON
交错的突发长度：2,4,8JESD-30 代码：R-PDSO-G66
JESD-609代码：e0长度：22.225 mm
内存密度：134217728 bit内存集成电路类型：DDR DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：66
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSSOP66,.46
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
认证状态：Not Qualified刷新周期：4096
座面最大高度：1.2 mm自我刷新：YES
连续突发长度：2,4,8最大待机电流：0.02 A
子类别：DRAMs最大压摆率：0.33 mA
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10.16 mm
Base Number Matches：1

HY5DU281622T-K 数据手册

 浏览型号HY5DU281622T-K的Datasheet PDF文件第2页浏览型号HY5DU281622T-K的Datasheet PDF文件第3页浏览型号HY5DU281622T-K的Datasheet PDF文件第4页浏览型号HY5DU281622T-K的Datasheet PDF文件第5页浏览型号HY5DU281622T-K的Datasheet PDF文件第6页浏览型号HY5DU281622T-K的Datasheet PDF文件第7页 
HY5DU281622  
4 Banks x 2M x 16Bit Double Data Rate SDRAM  
PRELIMINARY  
DESCRIPTION  
The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited  
for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is orga-  
nized as 4 banks of 2,097,152x16.  
HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all  
addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data  
strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The  
data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage  
levels are compatible with SSTL_2.  
Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 ), the number of consecutive read or  
write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or  
interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled  
through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved  
than that of traditional (single data rate) Synchronous DRAM.  
FEATURES  
•
2.5V VDD and VDDQ power suppliy  
•
Delay Locked Loop(DLL) installed with DLL reset  
mode  
•
All inputs and outputs are compatible with SSTL_2  
interface  
•
•
•
•
•
•
Write mask byte controlled by LDM and UDM  
Bytewide data strobes by LDQS and UDQS  
Programmable CAS Latency 2 and 2.5 supported  
Write Operations with 1 Clock Write Latency  
/QFC & Half Strength Driver controlled by EMRS  
•
•
•
JEDEC standard 400mil 66pin TSOP-II with 0.65mm  
pin pitch  
Fully differential clock operations(CLK & CLK) with  
100MHz/125MHz/133MHz  
All addresses and control inputs except Data, Data  
strobes and Data masks latched on the rising edges  
of the clock  
Programmable Burst Length 2 / 4 / 8 with both  
sequential and interleave mode  
•
•
Data(DQ) and Write masks(LDM/UDM) latched on  
both rising and falling edges of the Data Stobe  
•
•
•
Internal four bank operations with single pulsed RAS  
Auto refresh and self refresh supported  
4096 refresh cycles / 64ms  
Data outputs on LDQS/UDQS edges when read  
(edged DQ) Data inputs on LDQS/UDQS centers  
when write (centered DQ)  
ORDERING INFORMATION  
Part No.  
Power Suppy  
Clock Frequency  
Organization  
Interface  
Package  
HY5DU281622(L)T-K  
HY5DU281622(L)T-H  
143MHz (*PC266A)  
133MHz (*PC266B)  
125MHz (*PC200)  
VDD=2.5V  
VDDQ=2.5V  
4Banks  
x 2Mbit x 16  
400mil 66pin  
TSOP II  
SSTL_2  
HY5DU281622(L)T-L  
* (L) Low Power Part  
* JEDEC Defined Specifications compliant  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 1.2 / Mar.00  
1234567...10

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