HY57V651620BLTC-75

更新时间： 2024-09-14 22:36:35

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
12页	83K
描述
4 Banks x 1M x 16Bit Synchronous DRAM

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HY57V651620B

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

T h e H y n i x H Y 5 7 V 6 4 1 6 2 0 H G i s a 6 7 , 1 0 8 , 8 6 4 - b i t C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e m a i n m e m o r y a p p l i c a t i o n s w h i c h

require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1, 048, 576x16.

HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input a n d o u t p u t

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1, 2, 4, 8 or Full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Auto refresh and self refresh

•

Single 3. 3± 0 . 3 V p o w e r s u p p l y ^{N o t e )}

4096 refresh cycles / 64ms

All device pins are compatible with LVTTL interface

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

J E D E C s t a n d a r d 4 0 0 m i l 5 4 p i n T S O P - I I w i t h 0 . 8 m m

of pin pitch

•

All inputs and outputs referenced to positive edge of

system clock

•

P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks

•

D a t a m a s k f u n c t i o n b y U D Q M o r L D Q M

Internal four banks operation

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

H Y 5 7 V 6 5 1 6 2 0 B T C - 5 5

H Y 5 7 V 6 5 1 6 2 0 B T C - 6

H Y 5 7 V 6 5 1 6 2 0 B T C - 7

H Y 5 7 V 6 5 1 6 2 0 B T C - 7 5

H Y 5 7 V 6 5 1 6 2 0 B T C - 8

H Y 5 7 V 6 5 1 6 2 0 B T C - 1 0 P

H Y 5 7 V 6 5 1 6 2 0 B T C - 1 0 S

H Y 5 7 V 6 5 1 6 2 0 B T C - 1 0

H Y 5 7 V 6 5 1 6 2 0 B L T C - 5 5

H Y 5 7 V 6 5 1 6 2 0 B L T C - 6

H Y 5 7 V 6 5 1 6 2 0 B L T C - 7

H Y 5 7 V 6 5 1 6 2 0 B L T C - 7 5

H Y 5 7 V 6 5 1 6 2 0 B L T C - 8

H Y 5 7 V 6 5 1 6 2 0 B L T C - 1 0 P

H Y 5 7 V 6 5 1 6 2 0 B L T C - 1 0 S

H Y 5 7 V 6 5 1 6 2 0 B L T C - 1 0

1 8 3 M H z

1 6 6 M H z

1 4 3 M H z

1 3 3 M H z

1 2 5 M H z

1 0 0 M H z

1 8 3 M H z

1 6 6 M H z

1 4 3 M H z

1 3 3 M H z

1 2 5 M H z

1 0 0 M H z

N o r m a l

4 B a n k s x 1 M b i t s

x 1 6

4 0 0 m i l 5 4 p i n T S O P I I

L V T T L

L o w p o w e r

N o t e : V D D ( M i n ) o f H Y 5 7 V 6 5 1 6 2 0 B ( L ) T C - 5 5 / 6 / 7 i s 3 . 1 3 5 V

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

R e v . 1 . 9 / A p r . 0 1

12 3 4 5 6 7...12

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与HY57V651620BLTC-75相关器件

型号	品牌	获取价格	描述	数据表
HY57V651620BLTC-75I	HYNIX	获取价格	暂无描述
HY57V651620BLTC-7I	HYNIX	获取价格	Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V651620BLTC-8	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V651620BLTC-I	ETC	获取价格	4Mx16\|3.3V\|4K\|6/7/75/10P/10S\|SDR SDRAM - 64M
HY57V651620BLTC-P	ETC	获取价格	x16 SDRAM
HY57V651620BLTC-S	ETC	获取价格	x16 SDRAM
HY57V651620BTC	ETC	获取价格	4Mx16\|3.3V\|4K\|H\|SDR SDRAM - 64M
HY57V651620BTC-10	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V651620BTC-10P	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V651620BTC-10PI	HYNIX	获取价格	Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

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