HY57V651620B
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hyundai HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Note)
•
•
•
Auto refresh and self refresh
•
•
•
Single 3.3±0.3V power supply
4096 refresh cycles / 64ms
All device pins are compatible with LVTTL interface
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
All inputs and outputs referenced to positive edge of
system clock
•
Programmable CAS Latency ; 2, 3 Clocks
•
•
Data mask function by UDQM or LDQM
Internal four banks operation
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V651620BTC-55
HY57V651620BTC-6
HY57V651620BTC-7
HY57V651620BTC-75
HY57V651620BTC-8
HY57V651620BTC-10P
HY57V651620BTC-10S
HY57V651620BTC-10
HY57V651620BLTC-55
HY57V651620BLTC-6
HY57V651620BLTC-7
HY57V651620BLTC-75
HY57V651620BLTC-8
HY57V651620BLTC-P
HY57V651620BLTC-S
HY57V651620BLTC-10
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
Normal
4Banks x 1Mbits
x16
400mil 54pin TSOP II
LVTTL
Low power
Note : VDD(Min) of HY57V651620B(L)TC-55/6/7 is 3.135V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.8/Mar.01